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Power supply sequence

		
	
				

			

									
					    S1640
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Feb 15, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user inquired about the power-up sequence for VDD and VLOGIC and the impact of applying SPI signals before power-on. The final answer confirms no specific sequence is required for VDD and VLOGIC due to the POR circuit, but SPI lines must be kept in high impedance during power cycles to prevent erratic behavior through ESD diodes.
                        	    

                
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Category: Hardware

    		        		            		    
Product Number:  AD5674R  

    		        		    		    

		    		    
		    			

			    
Hi,

Thank you always for your great support.
I would like to confirm the subject of the device mentioned above.

Are there any restrictions or recommendations regarding the order in which the VDD and VLOGIC power supplies should be turned on/off? (The datasheet does not mention this.)
Also, are there any problems if SPI-related signals are input before the power is turned on?

I understand that there are probably no restrictions on the order of the VDD and VLOGIC power supplies, but I understand that the SPI signals will fall below their rated voltage if the VLOGIC power supply is not turned on. Is this understanding correct?

Best regards,

			

			
									
		                             
                        

    

                                            
                 D/A Converters (DAC)
                
                                                    
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                 Voltage Output D/A Converters
                
                                                    
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Feb 19, 2026 5:22 AM
            
            
						
			            		
    
		
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    There is no restriction in the sequence of VDD and VLOGIC because the chip incorporates a POR circuit that keeps it reset until both supplies are up. The order may have an effect in the power-up glitch produced on the VOUT pins.
    

    However, there must be no voltage in SPI lines during a power cycle. Otherwise, the chip gets supplied from the digital lines through the ESD diodes and it never resets. This can cause erratic behaviour. It is advised to keep the digital lines in high impedance during a power cycle.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Feb 19, 2026 5:22 AM
            
            
						
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    There is no restriction in the sequence of VDD and VLOGIC because the chip incorporates a POR circuit that keeps it reset until both supplies are up. The order may have an effect in the power-up glitch produced on the VOUT pins.
    

    However, there must be no voltage in SPI lines during a power cycle. Otherwise, the chip gets supplied from the digital lines through the ESD diodes and it never resets. This can cause erratic behaviour. It is advised to keep the digital lines in high impedance during a power cycle.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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