Power supply sequence

Question

Hi,

Thank you always for your great support.
I would like to confirm the subject of the device mentioned above.

Are there any restrictions or recommendations regarding the order in which the VDD and VLOGIC power supplies should be turned on/off? (The datasheet does not mention this.)
Also, are there any problems if SPI-related signals are input before the power is turned on?

I understand that there are probably no restrictions on the order of the VDD and VLOGIC power supplies, but I understand that the SPI signals will fall below their rated voltage if the VLOGIC power supply is not turned on. Is this understanding correct?

Best regards,

Antonius · Accepted Answer

There is no restriction in the sequence of VDD and VLOGIC because the chip incorporates a POR circuit that keeps it reset until both supplies are up. The order may have an effect in the power-up glitch produced on the VOUT pins. 
 However, there must be no voltage in SPI lines during a power cycle. Otherwise, the chip gets supplied from the digital lines through the ESD diodes and it never resets. This can cause erratic behaviour. It is advised to keep the digital lines in high impedance during a power cycle.)

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Power supply sequence

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