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AD5665R hook-up and message structure.

Thread Summary

The user seeks verification of the setup and I2C commands for a DAC chip. The final answer confirms the I2C address (0x3E) and the sequence of commands for power-on reset, power-up, enabling the internal reference, and writing to DAC A output. The chip is configured with ADDR1 and ADDR2 grounded, and the engineer has verified its functionality with external reference setup.
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Category: Software
Product Number: AD5665R

We have the chip connected as follows:
Pin 1 (LDAC) -> GND
Pin 2 (ADDR1) -> GND
Pin 3 (VCC) -> 5v
Pin 4 (VoutA) -> setup to read voltage
Pin 5 (VoutC) -> No connect
Pin 6 (POR) -> GND
Pin 7 (VrefIn/VrefOut) -> GND through a cap
Pin 8 (ADDR2) -> GND
Pin 9 (CLR) -> 5v
Pin 10 (VoutD) -> No connect
Pin 11 (VoutB) -> No connect
Pin 12 (GND) -> GND
Pin 13 (SDA) -> I2C Bus
Pin 14 (SCL) -> I2C Bus

First I'd like verification that based on ADDR1 and ADDR2 grounded and we're sending WRITE commands the correct address is: 0x3E

Then during our initialization we are sending 0x28, 0x00, 0x01 for a power on reset. Next we send 0x20, 0x00, 0x01 for Power-up. Then we send 0x38, 0x00, 0x01 to turn on the internal reference.

To set the DAC A output we are sending 0x58, (MSB), (LSB).

Can you please confirm that we have the proper hook-up and the proper messages? My EE claims he's set the chip up for external and verified that worked then set it back. He belive's this verifies the chip is functioning.

Thanks,
Brent