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AD569

Category: Hardware
Product Number: AD569

Hello,

I made a prototype of programmable and accurate power supply. It generates a voltage from 0.0000 V to 6.5535 V with 0.0001 V resolution.

There are MCU Freescale MC68HC908AZ60, 5 digits display and keyboard.

It used an AD569BD from old stock (date code 9142).

Power supply is +-12V from voltage regulators.

Vref + is adjusted near +5V. Vref - is adjusted near -1.7V

CNA-Vout of 5V gives 0.0000V output

CNA-Vout of -1.7V gives 6.5535V output

It works, but not very well ! There are abnormal things when the voltage is between 6.4V and 6.5535V. A second AD569BD gives similar things. The six lasts segments (internal resistors array) have a great error. The last segment has a resolution near from 1mV in place of 0.1mV.

X grid correspond to segment switching. Only the ten lasts segments are viewable on this diagram. There is no great errors from 0 to 6.4V.

I tried some thing :

- verifying stability of supplies, Vref+, Vref- and Vout on AD569.

- use and not use of Vref senses.

- verifying there is no noise and no oscillation on Vout

- verifying the accuracy of Vout : it has the same errors than the output voltage

- verifying the binary code input (only at 0 and $FFFF)

Now, I do not know what to do ? Is it a bug of AD569BD ? Is it too old ?

Thank you for any help.

John

  • Hi John,

    A couple of questions,

    1.Could you let us know what load you are trying to drive, or if you are measuring directly at the DAC output?

    2.Regarding the graph, could you clarify what the Y‑axis and X‑axis represent?

    3.Since you observe abnormal behavior only between 6.4 V and 6.5535 V, it would be very helpful to confirm whether the reference is really stable in that region. Have you already measured the reference voltage while stepping through those codes?

    4.What is the update rate of the DAC codes? 

    Thanks,

    Juan

  • I JGarcia,

    Thank you for this reply.

    1 - The load:

    The load of the DAC was only an AOP (LF156) wired as differentiel amplifier (Av = 1). R value is 100 kOhms. Then, I added a 12 kOhms resistor to GND, but this did not change anything.

    2 - The graph:

    X axis is the wanted voltage at the output in Volts. 

    Y axis is the error in % of Full scale range = 100 * (measured V - wanted V)/6.5536. All in Volts.

    3 - Stability of references

    Today, I redo the measures from 6.0926V to 6.5535V each 25.6mV. Vref+ and Vref- controled at each measure point. They was perfectly stable.

    4 - The max update rate is 5 per second. The timing used is the "Case A" of the datasheet. 

  • Hi,

    The error that you are getting is expected, please refer to Figure 4.
    The typical linearity error across the entire output range is within ±0.01 percent of full scale.
    %FSR = 100 x (0.001 / 6.5535 V) = 0.015258 %FSR
    This is the expected error that you will see at the DAC output. The 0.001 V corresponds to the 1 mV error you observe in the system.

     

    Let us know the requirements for your system and we can recommend a better part number for you.

    Thanks,

    Juan

  • Hi Juan,

    I think there is a mistake. The measured error was up to 2.8% of FSR, greater than the specification. The last segment (MSB code $00) had a slop of 1mV per lsb instead of 0.1mV per lsb.

    After some tests, I think the default is located near the Vref - sense. The AOP that regulates Vref- had a feedback current of 50µA throw the sense pin.

    Today, I modified the gains and reference voltages. The references was +5V and -1.7V and the output amplifier gain was 1. After modifications, the references voltages become +5V and -4.6V. The output amplifier gain becomes 0.681. In the same time, the feedback current into Vref- sense decreases from 50 to 28µA.

    Lasts measurements show less great errors :  

    Only 0.8% of FSR instead of 2.8%.

    At the moment, I do not know if the improvement is due to Vref- that changes from -1.7V to -4.6V, or due to the decreasing of feedback current.

    I think adding a buffer between Ref- sense and regulator, in order to decrease feedback current to 0µA. 

    Have a good day.

    John

  • Hi,

    Today, I added an OP177 as buffer between Vref- sense and voltage regulator. The feedback (sense) current is now lower than 0.003µA.

    Very good results ! The integral nonlinearity is now ok, even if I did not measurements for all the 256 segments.

    Thanks.

    John

  • Hi John

    Hi John - Good news then, your findings make sense. The AD569 relies on the Kelvin‑connected +VREF and −VREF Force and Sense pins to keep the reference voltage accurate at the internal resistor string. If any microamps flow through the VREF sense pin, the voltage drop across the internal or external series resistance translates directly into a gain and INL error.
    Buffering the VREF is a configuration recommended in the datasheet, which uses a precision buffer amplifier for the reference and keeps the sense current as close to zero as possible so that the DAC has a clean and stable reference at the Sense pins.

    If you are okay with using the AD569, that is fine. Otherwise, let us know about the requirements for your system and we can recommend a suitable part number for you.

  • Hi Juan,

    I am pleased to use this DAC AD569. It works well ! For the present, this is only a prototype. I do not know if there will be other production. 

    The specifications are (for this power supply) :

    - 16 bits monotonicity

    - 16 bits resolution with good INL.

    - low noise

    - settling time specification : lower than 100ms

    Have a good day !

    John