I’m working with the AD3542R DAC and noticed a mismatch between the advertised update rate and the actual achievable throughput over SPI. The datasheet specifies a maximum update rate of 16.5 MUPS, but the SPI clock is limited to 66 MHz. Even in dual SPI DDR mode, this only provides 132 Mbps, which translates to a maximum of ~8.25 MUPS for 16-bit updates and ~5.5 MUPS for 24-bit updates.
This suggests that the full 16.5 MUPS rate cannot be achieved using the DAC’s only supported interface. Could you clarify whether this update rate is achievable in any practical configuration, or if it reflects only the internal DAC core capability? If SPI is the only input path, would you consider revising the datasheet to better reflect the realistic throughput limits?
Thank you for your support.
