Issue with AD5700 recognizing the start bits of Preamble

Mind you i was using A5191HRT in the same associated circuit and everything was fine, this is the curve from that circuitry -

That is no delay before translation.

I also just saw that i have left decoupling caps on Vcc and IOVcc. But it was a recommendation in the Datasheet. (REG_CAP and REF pin caps are connected)

Plus, i can see that UART to HART conversion is alright. There's an issue with HART to UART only.

Hi Dave0101 ,

Can you provide a schematic and/or pin conditions of the AD5700-1?
Also, does this happen with every transaction? Or in a specific condition?
Kindly provide us with more information so we can investigate further. Thank you!

Regards,
Flynn

Can you provide a schematic and/or pin conditions of the AD5700-1?

My circuit is a copy of this - 

Only difference is the HART_OUT circuit as i had ported from A5191 but this HART_OUT section is sorted as i can see messages work fine other way around i.e. UART to HART is fine (I used a 3rd party HART sniffer on HART_OUT to check that DATA received is good)

It's just HART to UART which is tripping somehow.

Also, does this happen with every transaction? Or in a specific condition?

It is repeatable i.e. it starts translating from a particular place every single time. (I have used STM32, separate MCU and a UART sniffer to verify)

PS:

I did more testing and discovered more things  - 

I am using Linear Voltage Regulator to keep hart voltage at 18.5V, i tried changing that to a different power supply coming from a different board. Now preamble is visible 10% of the time somehow which makes me think it is something to do with the power side of things ?

ONTO my previous comments about lack of decoupling caps -  i added those caps but no difference. I still think it is something to do with the power side of things but cannot see anything wrong with any tracks or schematic.

Hi,

This issue is acknowledged and queued for support. Thanks for your patience.

Best regards,

Den

More on above, i am using external clock and i saw that clock is somewhat behaving a bit weird - 

It seems it is changing from Sine wave to Triangular form; this might explain why preamble gets missed if it is having sync issues in the beginning. Could this be the answer.

I am using ABLS-3.6864MHZ-L4Q-T but is the IC itself turning off the clock unless data is received?  (Is there some sleep mode in the IC which is enabled if there is no data transfer for a while ?)

Following up on this.

I tried removing the crystal and using the internal clock but same issue so probably not a clock issue.

Hi dendalisay , Any update on this ?

You say you are using an external *clock* but the part you mention is a *crystal*. Are you configuring the clock circuit for an external CLOCK input or to use the crystal oscillator? i.e. is nXTAL_EN = 1 or =0? Your other notes about power issues suggest that may also be a significant issue - but without circuit diagrams, no one can give you much help!