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SPI Communication with Nucleo L476RG. Doesn't work

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Category: Hardware
Product Number: AD5766sd2z, AD5766

Hi All.
I've connected my MCU board (Nucleo l476rg) to the DAC and I supply the power to the DAC from my MCU (its important for me) I want to get output range between 0-5 V. 
Im trying to control the DAC with SPI (mode 0) Commands that I send from my MCU using HAL function  HAL_SPI_Transmit(&hspi2, data, 3, HAL_MAX_DELAY); data[3] = 0x20,0xFF,0xFF. in order to read ~5v in ch 0 output.
I wired the DAC as follow:

        

the LK are:

I prefer to not use ADP5071 because I don't really get it.

It didn't worked for some reason.

after checking the output signal from MCU with scop I can confirm its Valid and seems legit.

I addition I can see all the expected voltage in the red checking points. 
I would really appreciate any help or suggestion. maybe there is something Im missing out. 
 THNX in advance.  

Edit Notes

forgot the LK configuration
[edited by: Bnaya at 1:15 PM (GMT -4) on 24 Jun 2025]
  • Hi  

    Thank you for using AD5766.
    Since you have the full evaluation kit, have you tried following the user guide? What problems did you encounter?

    I also want to clarify if the VLOGIC has a correct supply. In the first photo, it is unconnected.
    In the second, it is connected to external source. Does this mean that it is not connected to the MCU but still has a 3.3V supply? If so, then there's no issue there.

    The data you sent seems correct but please make sure of the compliance in the timings and polarities of the serial interface.

    Regards,
    Flynn

  • Hi. Thank you for the quick answer. I really appreciate it.
    Im not sure to what do you mean by full evaluation kit, I have the EVAL-AD5766SD2Z-5767SD2Z card as well as the nucleo MCU. 

    The VLOGIC at J10-6/12 isnt connected to 3.3v because Ive understand that J12-1 can be used for the VLOGIC as well. in addition while i wired 3.3v at J12-1 I could read 3.3 v from J10- 6/12.

    all the power supply comes from the MCU pins, 5v pin for the AVDD and 3.3V pin for AVCC and VLOGIC (same J12-1 port in the DAC board).

    about the compliance of the timing and polarity, as I mentioned is at mode 0 which means that the data sent at the rising edge of the clock (Low clock phase) and the clock is at 1.25Mbit/s. Is this configuration correct?

    In addition I would like to understand what is the different between the DAC register and the input register? i didn't find an explanation for it, i guess Ive missed it.     

    thanks again, Bnaya  
     

  • Hi  

    Can you send a sample of your SPI transaction for easier checking? Thank you.

    With regards to the difference between input register and DAC register, the input register temporarily holds the data that you want to write to the DAC register while the DAC register uses this data to update the output. An example purpose of this is to simultaneously update all DAC outputs in a single transaction (after writing to the input register).

    Regards,
    Flynn

  • Because I have only one bnc connecter i can show only one signal " live" and the second Ref A. In the attached photo ch Ref A is the clock and ch1 is the Mosi (input to the DAC board). 

    the signals are very "dirty" because I sample them with 2 pin probs. I believe the signal that the dac gets is clearer.   

    you can see the data says clearly 0x20ff

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