Is there a model or formula that can describe the output value of a DAC?

Hi,

Per a quick look at the MAX538 datasheet and considering standard DAC behavior, I think the output you're seeing is likely expected. This effect is often called a zero-code deadband, where the output stays flat for the first several digital codes. It’s mainly due to two factors in single-supply designs: (1) the amplifier's internal offset, which can attempt to drive the output below ground, and (2) the output stage’s footroom requirement, especially under load. The MAX538 datasheet highlights this by specifying linearity only from code 11 upward. Once the input code is high enough to overcome the deadband, the remaining deviation is mostly gain error, which explains why the actual/theoretical ratio gradually settles around 0.999 

 KevyU1212 , kindly provide more insight for this product. Thanks

Best Regards,

Den

Hi Den,

Thanks for your reply!

Under the current circuit configuration, what methods can be used to improve the DAC's output nonlinearity? Is there a formula or model that can simulate the actual output of the DAC? If so, I could incorporate this correction model into my program to reduce the error. 

dendalisay KevyU1212 Could you kindly provide some guidance? thanks.

Hi Miaowazhongzi ,

I echo what Den said in his previous comment. If you want to improve the output nonlinearity, only count code 11 and up so deadband won't be an issue. The datasheet suggests this is the result of a single supply part which I believe you are using. Since there is no negative supply, we won't know for sure the negative offset for the DAC. Other than switching to a DAC with dual supply like MAX531, you can check out this article: Open-Loop Calibration Techniques for Digital-to-Analog Converters | Analog Devices which provides ways to calculate and compensate for offsets.

Thanks,

Kevin

Hi Kevin,

Thank you for your reply. I’ve observed that the error shows both major and minor periodic trends, with Tminor = 64 and Tmajor = 256. Additionally, there is a linear downward trend both across the full range (0–4095) and within each major period (Tmajor).

Could this reflect a consistent internal pattern within the MAX538ACSA chip? Is it possible to describe this type of error using a theoretical model or formula, in order to improve the DAC’s output accuracy?

Thanks again.

Hi Kevin, 

Would you mind giving me some advice? thanks.

Hi Den,

Could you please give me some suggestions regarding the question raised on July 10, 2025? The specific content is in the loop above, thanks.