Hi,
I am currently working on an FPGA project involving ZynqMPSoC and SPI, and I wanted to check if there are any example register settings available for reference.
In our design, the dither pins are pulled down—do we need to account for this in our configuration, or can we leave them as-is without programming?
Additionally, could you share the relevant register settings for our setup? We are aiming for a voltage span of -5V to 5V, and any guidance on achieving this configuration would be greatly appreciated.
Looking forward to your insights.
Best regards,
Kausthubha K
Hi,
It's best practice to also programmatically power down the dither functionality. While grounding the pins correctly provides a 0V dither input, the dither blocks are enabled by default at power-on and should be powered down via software.
First, perform a SW Reset (recommended before setting the span ), next, Power Down Dither. Then, Set the Output Span to -5V to +5V, this configures the power-up condition P[1:0] to 00 (zero scale ) and span S[2:0] to 110 (-5V to +5V ).
To Write to a DAC Register, for example, to set DAC 0 to 0V within the -5V to +5V span (10V total span, VMIN = −5V, N=4096 for 12-bit): digital code D is calculated as 0V=(10V*D/4096)−5V, which gives D=0.5*4096=2048 (0x800). For the AD5767, this 12-bit data is placed in D15-D4 of the data field.
Br,
Den