Maximum Output Update Rate of AD3530 of all channels

Hi,

What's your specific application? The estimated max update rates for all 8 channels (for this example I've assumed of the application below), keeping in mind this is based on the figures and specs from the timing specs and assumes a 50 MHz SPI clock, CRC disabled, and that MULTI_INPUT_SEL_0 has already been programmed to target all eight channels and theb use input registers with a software LDAC for updates (to get faster results, tL4 ~1.3μs for LDAC vs t15 of typ 3μs for direct writes).The main things that determine how fast you can get new, stable voltages are basically the time it takes to send data to the chip (SPI comm),  DAC register updates to need about 640 ns of processing time between them, a typ 1.3 µs delay (tL4) before outputs start changing after LDAC, and ofcourse, the settling time.

For Common-Mode (all 8 channels -> same code):
Loading the 16-bit common word into MULTI_INPUT_CH (32 bits total: 16-bit instruction + 16-bit data) takes 32 × 20 ns = 640 ns. The subsequent 24-bit SW-LDAC command (16 bit instruction + 8 bit data) takes 24 × 20 ns = 480 ns, so SPI + LDAC = 1.12 µs. Adding the 1.3 µs tL4 delay + 5 µs settling -> Tcycle ~ 7.42 µs; with 12 µs settling -> Tcycle ~ 14.42 µs; giving ~ 134.8 ksps down to 69.3 ksps.

For Streaming Mode (all 8 channels -> unique codes):
Clocking 144 bits in one go/burst (16‐bit instruction + 8 × 16 bit data) takes 144 × 20 ns = 2.88 µs, + 480 ns for SW-LDAC = 3.36 µs total. Adding 1.3 µs (tL4) + 5 µs settling -> Tcycle ~ 9.66 µs; with 12 µs settling -> Tcycle ~ 16.66 µs; giving ~ 103.5 ksps down to 60 ksps.

Br,

Den