Maximum Output Update Rate of AD45335 all 32 Channels

Hi,

This can be determined by combining the SPI comm time with the settling time. Each channel's digital register can be updated via the SPI interface in approximately 0.8333 µs (which involves clocking in 19 bits at up to 30 MHz SCLK and a 200 ns recovery period between writes ), allowing for a maximum digital channel update rate of 1.2 MHz (as stated on the DS's timing specs as well).

What is the maximum update rate when only 1 channel is actively updated?: For a single channel, the effective update rate can be calculated as 1/(SPI Cycle Time+Analog Settling Time) but this varies significantly based on load conditions and the voltage step size (on spec table of DS for reference). For instance, the effective update rate can range from approximately 92.3 ksps (1/(0.8333 µs+10 µs using a 10 µs settling time for a 1 LSB rising edge step with no load ) down to about ~2.1 ksps (1/(0.8333 µs+470 µs) using a 470 µs settling time for a 1/4 to 3/4 full-scale falling edge step with a 200 pF load )

What is the update rate when all 16 channels are updated simultaneously?:These are addressed sequentially via the SPI bus, so the total SPI data transfer time amounts to 16 channels×0.8333 µs/channel≈13.333 µs. The effective group update rate for these 16 channels, once the last channel's output has settled (calculated as 1/(Total SPI Time+Settling Time of Last Channel)), similarly varies. It can be approximately 42.9 ksps (using 1/(13.333 µs+10 µs) if the last channel has a 10 µs settling time ) or approximately 2.07 ksps (using 1/(13.333 µs+470 µs) if the last channel requires 470 µs to settle ).

The primary factors influencing this basically include the output load capacitance the magnitude of the voltage step, and the device's inherent slew rate capabilities. It is recommended to minimize capacitive loads on the outputs, and always allow sufficient time for the analog outputs to fully settle before they are utilized in subsequent operations.

Br,

Den