We are unable to transfer data in dual SPI mode, writing data to the input register doesn’t result in output voltage (hardware LDAC is triggering). Despite us configuring the DAC to be in dual SPI mode, the alert pin becomes asserted when we write Dual SPI data with a partial data access error (INTERFACE_STATUS_A=2), and the transfer register reports we are in dual SPI mode.
When operating in classic SPI mode we see the alert pin assert after register writes with the error “invalid register access” (INTERFACE_STATUS_A=1); however, the write operation is still successful.
Here is how we are configuring the DACs:
1) Set reset_f to 0 and then we set it to 1, our GPIO delay accounts for the “held in reset”. This would reset DACs and then bring them out of reset.
2) Wait for 300ms to make sure DACs finish initialization after reset.
3) We don't have external pull-up for Alert pins on DACs. So we enable internal pull-ups by writing value of 0x44 into INTERFACE_CONFIG_D (address 0x14).
4) Clear INTERFACE_STATUS_A (address 0x11) and Error_Status_Register (address 0x17) by writing 0x01 to both of them.
5) For all 16 DAC chips do: Enable hardware LDAC (write 0 to HW_LDAC_16B and HW_LDAC_24B); Set output range to 0-5V (write 0x11 to CH0_CH1_OUTPUT_RANGE); Set external reference voltage (write 0x02 to REFERENCE_VOLTAGE_CONFIG).
6) Clear INTERFACE_STATUS_A (address 0x11) and Error_Status_Register (address 0x17) by writing 0x01 to both of them.
7) Enable Dual SPI mode by writing 0x40 to Transfer register at address 0x0F (setting MULTI_IO_MODE to 0b01).
8) Wait for 31 seconds in C# application and run the C application to read byte streams from a wavefile and write to DMA so that FPGA sends them to DACs over Dual SPI.
9) Once the 31 seconds wait in C# application is over, clear INTERFACE_STATUS_A (address 0x11) and Error_Status_Register (address 0x17) by writing 0x01 to both of them.
At the end, we see Alert pin is still asserted (at value 0) and INTERFACE_STATUS_A register has a value of 0x02.
We also noticed that before enabling Dual SPI, when using single SPI mode to write to any DAC registers for configuration, it would set INTERFACE_STATUS_A register to value of 0x01 and also assert Alert pins.
Here is an ILA for data transfer. The first time CS goes low, we send data to CH0_INPUT_16B register (for DAC0) and its MSB address is 0x34 and we send 16 bits of data (with value of 0x7FFF). We are using streaming mode with descending address. Then CS goes high and goes down again and now we send data to CH1_INPUT_16B register (for DAC1) and its MSB address is 0x36 and we send 16 bits of data (with value of 0x7FFF). Note that there is a bit of delay for LDAC and it goes low just before the next data transfer phase.
The signals in the ILA are as follows (from top to bottom): state, sdio[1:0], cs, ldac, clk, alert
