Reset for AD5592RBCBZ-1-RL7

Hi Techq ,

I'm going to move this to the (+) Precision DACs - EngineerZone community where they can help you better.

Thanks and regards,

Coco

Hi Techq ,

The AD5592R‑1 appears not to have a dedicated reset pin, so its gonna rely on a software reset via SPI. If you're concerned about SPI failures, due noise or bus contention, it's a good idea to add an external reset circuit if possiblesuch as a power switch or like a microcontroller-controlled load switch, so you can safely reinitialize or basicallu power cycle the device. I'm curious tho, could you tell me more about your application? 

Br

Den

Hi Den,

I have two slaves on the SPI bus, one of which is the AD5592R-1. Typically, I expect the SDO to be in a high impedance state when using external reset logic for the VLOGIC (assuming you mean the VLOGIC power reset). I want to ensure that turning the VLOGIC power of the ADC off and on doesn’t contaminate my SPI bus by having the SDO in an unknown state. Could you help me understand this better?

Hi Techq ,

Oh I see. So when VLOGIC is powered off, the AD5592R‑1’s SDO pin goes into a high impedance state, which means it won’t drive the SPI bus. This matches the datasheet’s “Floating-State Output Capacitance” spec of 10 pF, indicating the pin is meant to avoid interference when not active.

After powering VLOGIC back on, basically the device goes through a 250 µs POR, and during this time, SDO could brieflyoutput undefined data. To keep your SPI bus clean, wait at least 250 µs before resuming communication, and consider adding a pull-up resistor to SDO to prevent it from floating.

Br,

Den

Hi Den,

Thank you for confirming that the SDO remains in a high impedance state when VLOGIC is powered off.

Hi Techq ,

No problem. Just a quick note, the observation that SDO is likely in high impedance when VLOGIC is off is based on the datasheet’s “Floating-State Output Capacitance” spec of 10 pF, which implies the pin isn’t actively driven and should not interfere with the SPI bus. So to be on the safe side, I'd stilll recommend adding a pull‑up resistor to keep things stable during power transitions. Also, as I've mentioned before, after powering VLOGIC back on, wait at least 250 µs for the POR to complete. Closing this thread for now, but let me know if you have any more questions.

Br,

Den