We have a custom board with an STM32L031 connected to two AD5271 devices using a single SPI controller. The nSYNC pins are controlled by general purpose IO pins. The SCLK signal is 500 kHz. The design uses the internal pullup on the STM32 but an external 10k was added during debug without affect. The EXT_CAP should be connected to VSS but is connected to GND; however, connecting 10 uF from EXT_CAP to VSS didn't change the problem.
The RDAC registers can be read from both devices (referred to as R24 and R25). The first device addressed can have it's RDAC value changed and read back. Writing to the second device's RDAC seems to force the SDO pin low until a power-on reset.
Note that if R25 is written to first, R25 works as expected and writes to R24 fail. If R24 is written to first, then R24 works as expected and writes to R25 fail. It seems like the act of writing to the RDAC register causes the problem.
The image below shows both devices' RDAC being read, then the R24 device being written to (and verified) twice. The second write/verify cycle was intended to show that the write/verify cycle doesn't leave the SPI bus in a broken state. Next the R25 device is written to but fails the verify cycle. The SDO pin is held low.
This is the 2nd R24 RDAC register verify. It shows that the SPI bus is working properly.
The image below shows the SPI bus MISO stuck at ground during the control register write to enable the RDAC register:
The image below shows the RDAC register read also failing, most likely because SDO is stuck at ground.
Any suggestions on why a device is pulling SDO low when the chip select / nSYNC line is high would be great.
