Regarding the utilization of maximum update rate for AD5754R

Hello support team

Awaited your positive feedback on the above query. 

Hi Maitry ,

Thank you for reaching out. We are currently experiencing a high volume of inquiries, and responses may be delayed. Rest assured, we are queuing your question and   will get back to you as soon as possible.

Br,

Den

Hi Maitry 

Thanks for reaching out. 1MSPS is the digital interface update rate, but the analog output of the DAC reacts much slower than this. From the datasheet, table 3, settling time for 10V step is 8.5us max which is 117 kHz. You are getting around 155 kHz for a 5V step which seems close. 

So in order to maximiz the output data rate of a DAC we need to characterize the settling time to the exact or maximum voltage step in your application. We could further optimize this by removing the time delay of sending a 24-bit word to the DAC by matching serial write to the settling time timing. 

you can see the discussion on this thread. (+) Precision DAC sample rate - Q&A - Precision DACs - EngineerZone (analog.com)

Best regards,

Ian

Hi, 

I have gone through the link. 

As per DAC 5754R datasheet, DAC 5754R digital update rate is 1 MSPS. In the given link above: it is written " At best, you could achieve a 1MUPS output on a single channel on the AD5724R. ~0.25MUPS if you want 4 channels. "

This is same I am asking. If I want 4 channels, my digital update rate should be 0.25 MUPS. 

As per DAC datasheet, 0 to 5 V step, the settling time is approx. 6 usec. 

Now, If I want to maximize the output data rate of DAC, I need to characterize the settling time at 4 usec and I need to remove the time delay as well. that means 24 bit word of the DAC should be sending with zero delay.

my question is how can I achieve output data rate as 0.25 MUPS. and how can I reduce settling time to 4 usec (0.25 MUPS)?

what is the best possible practical achievable output data rate for DAC5754R if we could minimize the best possible settling time for DAC (0 to 5 V step response) and remove any further time delay for sending 24 bit word to DAC and match the serial write to settling time timing. 

Awaited your quick response. 

also, FYI: When we got 155 KHz , I found one observation which is wrong. at that time, accidently I have given same SCLK to DAC uploading data rate. which is not correct. so 155 KHz when I got is due to some random behiviour. 

Hello, 

I have further re-validated and follow the figure 2 of the datasheet for all the timings . With every 24 bit of data for individual DAC, My CS goes high with 162 ns and after transfer of all 4 dac data ( 96 bits), LDAC goes low after 130 nsec. 

my input data rate is 1 MSPS. My input is 0000 H , FFFF H, 0000 H, FFFF H, 0000 H, FFFF H .... and so on in a continuous manner. 

based on the above, I am getting output frequency of 130 KHz. that means, 2 updates within 130 KHz. so the we can consider it as 260 KSPS rate approx. right?

now, If I go with an individual DAC channel and do not use other 3 channels by removing the dependancy of LDAC. I might get 500 KHz output frequency. 

please review and provide your feedback weather my understanding is correct or not?

Hello,

I have also tried individual DAC update by disabling DAC channel 2, 3 and 4. My only single DAC channel is getting updated with 1 MSPS update rate.I have assumed it based on 500 KHz output frequency I am getting. below is the screenshot of the DAC channel 1 output. now my requirement is to go with individual DAC update one by one. My input module is generating continuous output with the rate of 1 MSPS for all 4 channel in a simultaneous manner. now I want to update each DAC channel one by one. 

1. 1st DAC 1 channel is getting input with a update rate of 1 MSPS. 

2. the next 24 bit data is for 2nd DAC at that time, DAC channel 1 should provide the same output from the previous given input. that means DAC channel 1 must be latched. 

3. the next 24 bit data is for 3rd DAC at that time, DAC channel 1,2  should provide the same output from the previous given input. that means DAC channel 1,2 must provide constant output based on the previous given 24 bit data inputs.

4. the next 24 bit data is for 4th DAC at that time, DAC channel 1,2,3  should provide the same output from the previous given input. that means DAC channel 1,2,3 must provide constant output based on the previous given 24 bit data inputs.

As () per this sentence, once the DAC channel 1 is getting latched it can provide DAC constant output till DAC channel 1 does not get new 24 bit data, right?

Hi, 

The scenario you pointed out above is correct, each dac channel would hold the value written to them. That means for a 1MUPS update rate, you are able to write to each DAC at 0.25MUPS. In theory, the maximum achievable frequency for a 2point square wave output with this update rate is half, which is around 125KHz. 

If you go back to using only 1 channel, with an updatre rate of 1MUPS, then the DAC theoretically, can reach 500kHz for a square wave output. This in practice would vary based on the voltage step and the capacitance in the load. It should be much lower due to settling time of this DAC.