AD5764 Output LPF on the EVAL-AD5764

Hi TanYL ,

 will take a look at this query and will get back to you soon.

Br,

Den

I tried to add a capacitor in the EVAL-AD5764 in C20 = 22uF and R14=56Ω and set the code from 0x8000->0x7fff, then I got this result. I found an oscillation in the output, although the glitch was suppressed. (the blue, channel 1 is the VoutD)

This oscillation becomes very obvious when the code is set from 0x8000->0x8010. (the blue, channel 1 is the VoutD)

so, my question is how do I choose the capacitance and resistance for C20 and R14 in EVAL-AD5764.

Thank you.

I suppose this is because there is equivalent inductance between the DAC output and the capacitor, if I add a small resistor(for example 10Ω) between the Vout and Capacitor, I think the oscillation can suppress. But it seems three is no space for that. Do you have suggestions?

Hi TanYL 

The R and C slots at the DAC outputs is meant to simulate load resistance and capacitace for the AD5764. 22uF is too large a capacitance load for the integrated output buffer on the chip. This is the primary cause for the huge oscillations seen a the output signal. If you need to drive a large capacitor at the output, you would need a capacitive load stable buffer. 

The glitch energy mentioned in the datasheet was taken with a 200pF and 10kohm load. This DAC has relatively low glitch energy. 

One more thing that could be affecting the glitch you are seeing at the output is due to the layout and probing technique. If you update the DAC using the same code, the only artifact left on the signal is the digital feedthrough.

I suggest, adjusting the load capacitance you have to something way smaller than 22uF. Series R (10-50ohms) would also work, you could put it outside the eval board and it would still work as intended.  

Best regards,

Ian

Hi Lan,

Thank you so much for your reply.

Thank you for telling me the function of the R and C, I have tried to adjust the C value from 22 uF(0603) to 10 uF(0603),  1uF, 100nF, 22nF and 2.2nF. Except for 2.2nF, the oscillation still occurred obviously. I use a 50ohm for the R. The code is set from 0x8000->0x7FFF.

For example, the 2.2nF situation. The oscillation occurred slightly. (ch1 blue is the the Vout.) 

And here is the 470pF situation. (ch1 blue is the the Vout.)

My primary purpose is to use the R and C slots to suppress the glitch. It seems it will cause oscillation. So it means that I should not use it in this way. I will also check the capacitive load stable buffer.

Unknown said:

The R and C slots at the DAC outputs is meant to simulate load resistance and capacitace for the AD5764. 22uF is too large a capacitance load for the integrated output buffer on the chip. This is the primary cause for the huge oscillations seen a the output signal. If you need to drive a large capacitor at the output, you would need a capacitive load stable buffer. 

Maybe it is true that it has a relatively low glitch energy.  But in my application, I think it is still too large. So I want to suppress the glitch.

Unknown said:

The glitch energy mentioned in the datasheet was taken with a 200pF and 10kohm load. This DAC has relatively low glitch energy. 

I test the glitch for the same updating code using 0x7fff without inserting R and C but using a 10MHz cutoff-frequency LPF in the probe. I can see the gitch in this figure. (ch1 is Vout, ch2 is nLDAC, ch3 is nSYNC). If this glitch is the digital feedthrough, how can I reduce it? I hope the output will not fluctuate.

for your final suggestion. I have also tried to add an LPF outside the eval board. 

The result is shown in the diagram below by setting the code from 0x8000->0x7fff.

I can see the glitch is suppressed. However, some high-frequency components occurred in the output. As shown below, its period is about 11.5us. I think it is from the environment. The SCLK is 20MHz here.

So, if I move this circuit very close to the chip and use chip capacitors and resistors, will I get better performance?

Thank you.

Hi TanYL 

First, I think the Rload (56 ohm) is too much for the device to handle. The AD5764 has a 10mA short circuit current (5mA by default). Are you able to get the proper midscale output value? (~5V)

If you redesign the circuit, make sure to also consider properly isolating the digital return paths from the analog output side. From this plot that you sent R and C load, it looks like the vout is reacting to the edges of the digital signals. This points to noise coupling from the digital signals or the digital block, commonly via ground coupling. 

The LPF circuit response would improve once you move it closer to the device. Please try and check where the HF noise comes from, could be from the probes or the probe grounds. 

Best regards,

Ian

Hi.

Thank you very much for your reply.

I also found that the 56ohm resistor would pull down the Vout. Thank you. If I use the 56ohm resistor connected to the ground, The maximum output could reach only 500mV for 0xFFFF(It should be 10V) . So I remove the 56 ohm resistor.

Unknown said:

First, I think the Rload (56 ohm) is too much for the device to handle. The AD5764 has a 10mA short circuit current (5mA by default). Are you able to get the proper midscale output value? (~5V)

Do you mean I should isolate the SCLK, nSYNC, SDIN, and nLDAC? I use FPGA IO to connect to the EVAL board in this test. And I add an Icoupler chip (ADuM260) to separate the FPGA GND from the DAC EVAL board DGND. I found that the schematic of this EVAL board about the AGND and GND connection is a ground link. Can you tell me in detail what is the groundlink?

Unknown said:

If you redesign the circuit, make sure to also consider properly isolating the digital return paths from the analog output side.

Thank you, I understand this point.

Unknown said:

This points to noise coupling from the digital signals or the digital block, commonly via ground coupling. 

Thank you. I tried to measure the glitch by removing all other probes but keeping the glitch measurement probe.

Unknown said:

Please try and check where the HF noise comes from, could be from the probes or the probe grounds. 

The result is shown here. I keep updating about every 4.5 us using the same code 0x7FFF. I can see the glitch, about 6.8mV, which corresponds to the previous plot. I haven't found the cause of this noise so far. 

Sincerely,

tan