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DAC AD5680 output not matching requested value over SPI

Category: Hardware
Product Number: AD5680

Hi, I'm using the AD5680 DAC connected to a uC via SPI.

I can control the DAC correctly but periodically the device seems to enter a strange "mode" where the driven output voltage is only halt the requested one or stuck to a fix voltage.
The control can work for hours before starting to permanently misbehaving.
The only way to restore functionally is to power cycle the DAC.
I checked the SPI connection and all looks fine. Voltage reference and supply are stable.

Is there a way to restore functionality without powercycing?

The datasheet refers to "DAC modes". Is there a reference document or a way to get out of those modes?

  • Hi  ,

     is currently checking this query and will be getting back to you soon. Thanks

    Br,

    Den

  • Hi  

    Can you probe the SPI channels for when the DAC is operating correctly, and when the problem happens? Ideally, we'd want to see SYNC, SCLK, SDI and check on the timings. 

    Best regards,

    Ian

  • The SPI seems to be correct and we are driving it very slowly. I also checked the SPI with an oscilloscope to see the signal in more details.
    I think that sometimes, during transmission one of the reserved bit, a noise spike flips the data and transition the DAC in a strange mode.
    In this picture there are signals from two DAC but data and clock are shared. 

    When the DAC starts to misbehave the SPI commands sent to the DAC are the same both in the logic analyzer and oscilloscope view.
    We also tried our theory with a direct connection with a single DAC using an USB to SPI converter. If we send both of the SPI bit, that needs to be zero, to one instead the DAC stops working and doe not recover.

  • Hi  

    We should be careful with regard to reserved bits. Firs,t we need to address the accidental toggling of the reserved bits due to noise spikes in the SPI line. A good solution would be to place series R to suppress reflecting waves and to act as low pass filters for the unwanted spikes. 

    I don't have information on what state the device goes into when the reserved bits are triggered. This device doesn't offer any other reset feature that may help during lock-up. I think that only power cycling works. I'll try to see what I can find in the lab. 

    Best regards,

    Ian

  • Hi Ian,

    thank you for your reply. We are now trying to reduce the noise on the SPI interface with HW modifications. We can detect when the DAC stops controlling the output correctly but power cycling the device would mean restarting the whole embedded system. This would mean a down time of 10 minutes every time it happens. We are also considering moving to another part if we can mitigate/solve this issue with improved HW/SW.
    Kind regards.

    Daniele

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