Output is not changing when configure with SPI.

Hi Scientific ,

To help resolve your issue, please provide a schematic, scopeshots of SPI signals, and your SPI configuration details (clock speed, mode, etc.).

Br,

Den

Hi Scientific ,

To help resolve your issue, please provide a schematic, scopeshots of SPI signals, and your SPI configuration details (clock speed, mode, etc.).

Br,

Den

The SPI data frame is provided below

The SPI configuration is 500KHz is clock and 8-bit data transfer, SPI master mode. 

Hi dendalisay, 

can you help me to resolve the issue.

Hi Scientific ,

1.) As per checking with the diagram I can see that there's seem to be a data setup and hold time violations (SDI on the 18th bit is on the same edge as the clock). The scopeshot seems to be from a logic analyzer. Can you provide it using an oscilloscope? This way we can check the voltage levels?

2.) Can you clarify as the reference voltage as well?

3.) Another unknown that might be contributing to the issue is the the fact that the LDAC rising while CS is falling.

Best Regards,

Den

hi,

can you provide the waveforms for the same, so I can compare with my waveforms.

Thanks

Hi Scientific ,

You may refer to the timing diagram section of the datasheet. That will provide the proper data setup and hold time specifications that should be observed.

Br,

Den

hi,

we referred the same specification for hold time and setup time.

Thanks  

Hi Scientific ,

Kindly try changing SPI modes because as per checking with the attached shots I can see that there's seem to be a data setup and hold time violations (SDI on the 18th bit is on the same edge as the clock)

Br,

Den

hi, i am getting the output range from -1.6 to -3.3 for 3.3 voltage reference. for all input range from 0 to 65535.

Hi Den,

finally, we achieve the output as expected. Thank you for the kind help.

Thanks, and Regards

Rohit Jain