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SPI tyming

Category: Datasheet/Specs
Product Number: AD5686 quad DAC, AD5686

I'm a bit confused, given Maartenh's response in November 2021. I wants to 
know which is the best and fastest way to update via SPI the values to be converted of all four channels, with the timing of the SYNC control signals and then have their simultaneous and synchronous conversion via LDAC.

Best regards

Arturo Wolfsgruber 

  • Hi  ,

    Can you provide more context or link on the thread you mentioned that was on November 2021 so we can help clear the confusion? (if you are curious about the update rate of this DAC, you may check out this thread as well AD5686R Sample rate).

    Best Regards,


  • The link was :

    My goal is to generate syncronously 4 sinusoids, with 16 samples /sinusoid, at a maximum sinusoid frequency of 20kHz Needed transfer rate = 1.28 S/s.

    With 50MHz serial clock, 24 bit + Sync, each word are 500ns long. Every 4 words, with *LDAC after t14 = 800ns, means 2.8us or 1.6M samples/s. But if i must wait t9 = 830ns for every serialy transfered word, plus common *LDAC for the 4 words, means 1030ns  or 0,97M samples/s. Practicaly my SPI is working as the serial clock would be 30MHz.

    But why 830ns - 500ns = 330ns, a so long time, for a transfer from input shift register to the internal channel register?

    How is possible to optimize the serial data transfer, to maximize the syncronous update rate for the 4 channel? 

  • Hi  ,

    The time taken for a transfer is determined by the design of the DAC and the process technology used, making that "330 ns" a black box to us. To optimize the serial data transfer and maximize the synchronous update rate for the 4 channels, you could consider interleaving the updates to the four channels. This means updating one channel at a time. This would allow the other channels to be updated while one channel is settling, potentially increasing the overall update rate.

    However, it’s important to note that the maximum update rate is still limited by the DAC register update rate (T9). T9 effectively defines the maximum update rate of the DAC. There’s no problem with driving the clock at 50MHz, but the T9 min spec should be followed. This timing constraint ensures the integrity of the data being transferred to the DAC registers.

    You may read more here: Precision DAC update rate

    Best Regards,