Post Go back to editing

AD5592R three-state on channel 0 causing ADC channel reads corruption

Category: Hardware
Product Number: AD5592r

I am using AD5592R with a combination of ADC and Three-state channels as follows:


Channel 0, 1, 2, ... 7 configured as ADC channels:  - No problem on ADC sampling. 

Scenario 2: 

Channel 0, 1, 2, ... 6 configured as ADC channels and channel 7 configured as Three-state - No problem on ADC sampling and also Three-state output channel 7 is working perfectly.

Scenario 3: 

Channel 1, 2, ... 7 configured as ADC channels and channel 0 configured as Three-state - PROBLEM on ADC sampling However Three-state output channel 0 is working perfectly.

The problem comes after setting channel 0 to three-state. Then the ADC conversions just keep reading some garbage values, never come ADC sequential values as in scenario 1 & 2. 

If I set three-state on any other channel, other than channel 0, then ADC is working perfectly (similar to scenario 2)

Is there anything special on channel 0 setting to three-state resulting ADC sampling to corrupt?

Further to add, no problem on channel 0 three-state and DAC outputs on other channels - the issue seems only with the ADC.

  • I am running the SPI clock at 400 kHz which I was increased to 1 MHz however increasing the clock did not resolve the issue. Still channel 0 tri-state corrupts other ADC samplings.

    I set following registers in the order.

    1). SW Reset

    2). Tri-state config

    3). ADC config

    4). ADC Sequence

    5) NOPs to get ADC samples...

    back to point 1).

    Scenario 4: Here I am setting channels 3,4, 5 as ADC and channel 1 as Three-state - ADC sampling working perfectly.

    Please note: Bitscope logic analyzer shows endianness incorrectly . Here MOSI is with correct endianness and MISO is inverted, next image shows MOSI with incorrect endianness and MISO with correct endianness)

    Scenario 5: I am setting channels 3,4, 5 as ADC and channel 0 as Three-state - and now ADC sampling PROBLEM !

    This kind of a proof that the software code setting the registers are correct and the AD5592 acts differently when channel 0 is in Three-state.

    Appreciate your help to understand the issue here.

  • Hi  ,

    We're currently taking a look at this query and will get back to you soon. Thanks for your patience.

    Best Regards,


  • Hello Iasa,

    We have not been able to reproduce the issue you are facing.

    Please provide me the following details.

    1. Entire circuit diagram and the test conditions.

    2. Are you using an external reference? If yes, of what value?

    3. Entire register sequence after power up, including the /SYNC high period and the SCK frequency.