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Power-ON Glitch

Category: Hardware
Product Number: AD5755-1ACPZ, AD5755-1

Hello all,

We are getting a power ON glitch of about 1.2V on all DAC output channels of AD5755-1ACPZ IC. 

Attaching the Relevant Snippets of schematics given below;

We were able to reduce the glitch to around 500 mV consistently when an external 10 kOhm pull-down resistor was placed on the DAC output channel.

Is there any other way by which we can further reduce amplitude of the glitch?

Top Replies

  • Hi  ,

     is currently taking a look at your query and will get back to you soon. Thanks!

    Best Regards,

    Den

  • Hi  

    Can you give a scope shot of the glitch you are measuring? The ground probe should be as close to the AD5755-1 as possible. Datasheet only shows power on glitch of around 150nV-sec, see Figure 30 AD5755-1 (Rev. H) (analog.com). The DAC Outputs should power-up in tristate with POC=0. and the DCDC converter is also powered down during power up. 

    It might be something on your system that caused the glitch to reflect to the DAC Outputs. I suspect one of your supplies (AVCC, AVDD or AVSS) that might cause the glitch. 

    What's your power supply sequence used? Please also share the command line sequence for initialization. Something similar to Figure 76. 

    Best regards,

    Ian

  • Hi  ,

    Please see the below scope shots of the power sequence with glitch on the first channel. We have captured the below snapshots with nearby ground reference.

     

    We can see a glitch of around 1.2V for a period of less than 10mS.

     

    In the  above snap shots, AVSS = -15V, AVDD = +15V and AVCC = +5V.

     

    The AVCC, AVDD and AVSS are generated through regulators from the 3.3V supply.

     

    Currently, to debug the power on glitch issue, we have isolated/disconnected our card from the host system (so that there are no SPI transactions to the card) and we are supplying the card with 3.3V through an external supply.

    However, for the bring up tests that were conducted with our card connected to host system, we followed the command line sequences as per the figure 76 in the datasheet. We have maintained a 1sec interval between commands.

    1. To SW reset the DAC IC0 = 0x003C_8555
    2. To set INT_EN, DC_DC and range 0-5V = 0x003C_4110
    3. To set digital code to mid scale = 0x0020_0000 (set to 0V)
    4. To enable output of DAC = 0x003C_4150
    5. To set digital code to max scale = 0x0020_FFFF (set to 5V)

    Please let me know if you need more details on the same.

    Thanks !

  • Hi  ,

    Kindly request your review and response regarding the comment I have prepared. I would greatly appreciate your feedback and insights.

    Thank you for your time and consideration.

  • Hi  

    Thanks for sharing the plots. One thing I noticed from the original thread is that a 10kohm load improves the glitch performance. There is certainly a relationship between the two. The datasheet specs were tested with predefined load as well. 2k ohm and 220pF. 

    AVDD ramp seems to be peculiar, is there no way to put a UVLO here to control when the supplies turn on. Not when the main source 3P3 is still not stable. The slew rate of AVDD and AVSS would play a large role in the magnitude of the power on glitch as well. You can validate this by using controlled slew rate sources for AVDD and AVSS. 

    The command sequence should have no effect on the power-on glitch as well. I just had to check them. 

    Best regards,

    Ian 

  • Hi  ,

    1. I have tested with a 2kΩ and 200pF load on the DAC outputs, and I am getting a glitch amplitude of about 200mV in most of my trials. However, I can also see a 800mV to 1V glitch occasionally.

    2. Next, I tested by disabling the AVDD regulator(Load removed). Despite this, I can still observe a glitch with an amplitude of 0.6V.

    Please let me know you comments on this and anything else which i need to try on?

    Thank you!

  • Hi  ,

    I would greatly appreciate your response to my previous comment.

    Regards,

    Alwin

  • Hi  / ,

    I kindly request your attention to my observations !

    Please let me know you comments on the matter and anything else which i need to try on?

    Regards,

    Alwin

  • Hi  , 

    The glitch performance in the datasheet was measured with VBOOSTx tied to AVDD. Also in our measurements, there is specified control over the AVDD and AVSS ramp-up time. See below old data I was able to find on power on glitch.

    Best cases are always taken from the lab when the supplies are controlled by instruments. If you could try to do that in your setup so we can check what else may be affecting your power on glitch. 

    Q> In your application, do you use the outputs of the AD5755-1 as current or voltage outputs? 

    Best regards,

    Ian

  • Hi  ,

    Thanks for the response.

    I have checked by giving AVDD from a external source which causes the glitch to reduce to around 500 to 600mV. Further it is reduced to less than 50mV when i connected a load of 2kΩ and 200pF.

    Additionally, i checked by pulling up POC pin to 3.3V and that also reducing the glitch to less than 100mV without connecting load. I need to further explore on POC pin and its function.

    Kindly let me know your comments on the above observations.

    Q> In your application, do you use the outputs of the AD5755-1 as current or voltage outputs? 

    Ans> Yes, we were using both current and voltage outputs of AD5755-1 DAC.