Post Go back to editing

Enquiry for part AD5392BSTZ-5 (SO# 187426)

Category: Datasheet/Specs
Product Number: AD5392BSTZ-5, AD5392

Hi,

Customer needs the documents as below for customs clearance.

Per customer:

We require supporting documents in relation to or stating

      the following specifications for product, Analog Devices AD5392 8-channel,

      14-bit voltage output DAC:

      a)'adjusted update rate' (in mega samples per second (MSPS));

      b)'Spurious Free Dynamic Range' (SFDR) (in dBc) (carrier) when

      synthesising a full scale analogue signal of 100 MHz or the highest full

      scale analogue signal frequency specified below 100 MHz.

     

      Technical Notes

      1.'Spurious Free Dynamic Range' (SFDR) is defined as the ratio of the rms

      value of the carrier frequency (maximum signal component) at the input of

      the DAC to the rms value of the next largest noise or harmonic distortion

      component at its output.

      2.SFDR is determined directly from the specification table or from the

      characterisation plots of SFDR versus frequency.

      3.A signal is defined to be full scale when its amplitude is greater than

      -3 dBfs (full scale).

      4.'Adjusted update rate' for DACs:

      a)For conventional (non-interpolating) DACs, the 'adjusted update rate' is

      the rate at which the digital signal is converted to an analogue signal

      and the output analogue values are changed by the DAC. For DACs where the

      interpolation mode may be bypassed (interpolation factor of one), the DAC

      should be considered as a conventional (non-interpolating) DAC.

      b)For interpolating DACs (oversampling DACs), the 'adjusted update rate'

      is defined as the DAC update rate divided by the smallest interpolating

      factor. For interpolating DACs, the 'adjusted update rate' may be referred

      to by different terms including:

      _input data rate

      _input word rate

      _input sample rate

      _maximum total input bus rate

      _maximum DAC clock rate for DAC clock input.

      5.'Settling time' means the time required for the output to come within

      one half bit of the final v"

Please help to advise whether can support.

Thanks

Regards

  • Hi  .

      is currently checking this query and will get back to you soon.

    Best Regards,

    Den

  • Hi  

    for conventional DACs, there can be two ways to approach update rate. First one is to consider both the input data rate and the settling time. Second would be to disregard the input data rate and consider only the settling time. This is only possible if the input data rate is faster than the settling time. See the image below for an illustration. 

    For case 1) input update rate (time) @max clock frequency = t7+ t4 + 23*t1 + t21 = 754ns while settling time is 8us max, for an update rate of ~0.114 MSPS

    For case 2) settling time of 8us max for an update rate of 0.125 MSPS

    For SFDR, unfortunately we do not have data for this particular generic. 

    Best regards,

    Ian