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Unable to get a output voltage

Category: Hardware
Product Number: AD5721R

Im using the ad5721r DAC to controll the biasvoltage of a varktordiode (144 in total, DACs in Daisy Chain). For now i configured the DAC0 to unipolar mode 0-5V. Im not able to get any output voltage from the DAC (its always 0V). I attached an image of the SPI lines and the schematic.

First i send a Fullreset 0x0F followed by a write operation of the controll register 0x04063B. The readback operation shows a value of 0x0C063B which looks ok. The last step writes data (2000 counts) to the input register with automatic update of the dac register 0x037D00 (readback shows right value). This should force the output to Voutmax/2. But the output does not show anything. Vdd = 6V Vss = 0V  DVcc = 3.3V. SPI CLK 125 kHz. Vref Out = 2.5V. Nsync pauses 5us and 35us . 

Thank you in advance for your help.

Best regards,


D0 =  NSync 



1 = MISO (SDO0_SDI1)

D4 = NReset (always high)

  • Hi,

    We are currently checking this query and will get back to you soon.

    Best Regards,


  • Hi  ,

    Apologies for the late reply. Commands as per checking are all in order from the control register, readback to the writing. It seems readback values are also as expected. Troubleshooting in daisychain is a bit complex so i suggest starting with the isolation of a single DAC in the chain. Does the issue persist, or does it work correctly in isolation? 

    Also, just to be sure kindly try measuring Vdd, Vss, DVcc, and Vref directly at the pins of the first AD5721R in the chain. Ensure they are within datasheet specifications and are exceptionally stable.

    Best Regards,


  • Hi Den,

    thank you for your answer. Today I found out what went wrong. The problem is with the Control board I am using. In my case it’s a Nucleo-L432KC. This board provides a CustomUser LED attached to the SPI_CLK Line. This caused the Problem. I unsolderd the Jumper (SB15) and the DAC worked as intended.  A second option was to solder a series resistor in the CLK Line. Both worked for me. The only question is why the SPI transfer looked okay at all, especially the readback.


    Best Regards, 


  • Hi Armin,

    That's great news. I also find it weird since the SPI transfer looked rather fine, as confirmed via scope and logic analyzer. At the top of my head based on your findings and testing I can think of two possibilities. First, LED acting as a Load - LEDs, when active, act as a load on the signal line. This load can subtly distort the SPI clock edges, particularly during transitions, potentially violating the DAC's strict timing requirements for data latching on write operations. Second one is about the Clock Edge Sensitivity of the device. The AD572xR might be more sensitive to the integrity of a specific clock edge (likely the falling edge for data latching) during write operations. Solutions like disconnecting the LED or adding a series resistor make sense by either removing the source of interference or mitigating its impact.

    Best Regards,