Category: Datasheet/Specs
Product Number: AD5293
I have an FPGA controlling chains with eight of these digipots each. AFAICT it is working OK, but when looking at the timing charts (Figure 3 and Figure 4) to check some of the timings of the implementation, I noticed SCLK is either high or active (i.e., clocking), whereas in the FPGA implementation the idle state is low. Below is the screen shot of SYNC (top) and SCLK. The first SYNC sends a sequence of command 4 to all digipots in the chain to allow for wiper updates and the second SYNC sends the sequence of command 1 with wiper values of the chain.
Here is the timing from the the falling edges of SYNC to first rising edge of SCLK.
Here is the timing of the last falling edge of SCLK to rising edge of SYNC.
Is this OK?
