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ad5293 - SDO falling edge delay from SCLK rising edge.

Category: Datasheet/Specs
Product Number: AD5293

Figure 4 of the data sheet, t14, has a maximum value of 450ns, but no minimum. Though Figure 4 refers to Read Timing, I suppose it applies to daisy chaning as well. Now the 450ns must have to do, at least in part, with the 2.2k/168pF time constant and it makes sense for the low to high output transition of an open drain output, but what about the high to low transition? What is the delay? I measured ~10ns (note, only pins and relatively short tracks capacitance) but I would feel more comfortable with some manufacturer's figure.

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    •  Analog Employees 
    Feb 29, 2024 in reply to EVC2024 +1 verified

    Hi  ,

    There's no figures. Time constant can also be used in the equation for discharging as well given your initial voltage (Eo) = Digital supply and your desired capacitor voltage (Ec) = VIL.…

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