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How to enhance output frequency stability AD3551R?

Category: Software
Software Version: vivado 2022.1


Please help me with output frequency of AD3551R.

1. Input  to AD3551R sin_wave sample, I got the sin wave at output  DAC AD3551R but some variation in output such as

system_clk sclk Expected_output freq output frequncy Number
 of sample
100MHZ 25MHZ 2KHZ 1.85KHZ 520
200MHZ 50MHZ 2KHZ 1.85kHZ 1041
250khz 50Mhz 2KHZ 2.3khz 1041

Why such variation in the output ? what the DAC AD3551R precision ? How to achieve the correct 2khz at output ?

Thread Notes

  • The problem is likely with the controller or the generation of the samples. The sampling frequency is tightly related to the SCLK frequency with the formula:

    fs = fCLK * DR * DataLanes / 16

    This formula is for streaming mode with 16 bits per sample, that is the recommended way to transfer data for waveform playback. DR is 1 for SDR and 2 for DDR. DataLanes is the number of lines used for data transfer: 1 for classic SPI, 2 for dual SPI and 4 for QSPI.

    Example: with a clock frequency of 25 MHz, the sampling rate in Classic SPI SDR is 1.5625 MSPS.

    The number of samples per cycle is fs / f0 where f0 is the frequency of the tone.

    For example, a 2 kHz tone played at 1.5625 MSPS takes 781.25 samples. In this case 4 cycles are required to achieve perfect circularity of the samples and avoid phase steps that result in harmonic distortion. Other frequencies may require more cycles to achieve circularity, therefore a DDS is preferred versus a pattern memory.

  • Hello,

    I am using the SINGAL SPI

    1. For data writing:

    SDI===> CH0_DAC_16B: 0x2A (address) F0 (MSB_DATA)  F0 (LSB DATA) IN STREAMING MODE

    so I am consider the 24 bit

    this formula I am using 

     double voltage1 = sin(2.0 * M_PI * add_freq * time);

    As per your suggestion if I used 16 bit than I got the 

    I want precision of 2.000khz not 2.018 not 1.908 not 1.89khz. How to achieve it ?  

  • Streaming mode is a single register address followed by a continuous stream of data while CS is kept low. Every additional sample takes 16 bits only.


    Streaming mode requires previous configuration to enable this mode and configure the loopback address step.

    When playing a single sine wave cycle stored in memory, frequency resolution is not linear. The period of the sine wave can be incremented in steps of 1/fs. Only the frequencies that produce an integer number of samples can be reproduced. f ' = fs / round (fs / f), where f is the desired frequency of the tone and f ' is the closest frequency producing an integer number of samples.

    Another possibility is using a pattern containing several sine wave cycles, which gives more flexibility the selection of the frequency. Three examples are given in the following table:

    Clock Freq. Sampling Freq. Period in samples Tone Freq. Number of Periods in Buffer
    50 MHz 3.125 MHz 1562 2.00064 kHz 1
    50 MHz 3.125 MHz 1563 1.99936 kHz 1
    50 MHz 3.125 MHz 1562.5 2.00000 kHz 2

    When the period of the sine wave is not integer there is a possibility of approximating the number with the closest rational, where the denominator is the maximum length of the buffer. Certain frequencies may require quite a large buffer to achieve circularity.

    If you are limited in memory, you can use a DDS algorithm to produce the samples on the fly using a phase accumulator to index a a sine wave table.

  • hello,

    I write driver such that it cs goes high and low after 24 bit each like

    cs low: REG_ADDR MSB LSB after that cs high

    after second sample when cs low REG_ADDR MSB LSB again cs high. so consider 24 bit.

     ideally what should happen ? if we change the 1_2_3 LSB OF 16 BIT DAC ? in term of amplitude or frequency.

    Is there is any offset error that why it is not giving the exact 2.000khz at output ? 

  • If the controller is a CPU, there is an undetermined amount of time between frames, so it is difficult to achieve precise frequency.

    The minimum CS high time is 10 ns, but since SCLK is 40 MHz I assume that the minimum the CPU can do is one clock cycle, that is 25 ns. Looking at the numbers above it seems that the inter-frame gap is varying from 18 ns to 25 ns.

    If you had 24 cycles for the frame plus 1 cycle for the inter-frame gap, the sample frequency would be 40 MHz / 25 = 1.6 MSPS. This frequency is an exact multiple of 2 kHz, so you just need a single cycle of 800 samples.

    You may use DMA and streaming mode to improve the timing, but you can't stop the CPU from accessing the memory between DMA cycles, unless the device has a DP memory or the entire program is running in internal cache memory.

    For precision waveform generation we recommend using an FPGA.

  • Hello,

    I am using FPGA 

    ideal freq:1800hz ==> scope_freq 1720hz,  4500hz ===> scope freq 4295hz. why there is no stability in frequency.(system clk: 400Mhz and SPI clk: 40Mhz)

    where exact I am going wrong, please suggest something ?

    Would you please define the interframe gap? where should one cycle delay given ?

  • The inter frame gap is the time between two SPI transactions. You can check this parameter triggering on CS in envelope mode. If all the waveforms overlap nicely, your sampling rate is constant. If there is a spread in one of the edges, you sampling rate has jitter.

    I realize you are enabling 15-bit addressing in Config B register. This requires 32 bits for every transaction, but you are sending 24 bits.

  • Thank you so much for your help.

     Inter frame gap work to give the precision output frequency.