AD5754 DAC analog output always updated one value behind

Hi,


We have a board with two AD5754 daisy chained together.

Both LDAC pins of those two AD5754 ICs are tied to ground permanently (hardwired).

Offset binary is used for DAC coding.

Power up sequence is respected, so DVcc is powered before AVss AVdd, then output range is selected through SPI (+/- 10V bipolar), then channels are powered up. Everything works up to that part.


However, when updating the DAC outputs, say I send through SPI some 24-bit value to update all DAC outputs to "-5.85V".

Assume initially the DAC output is at 6.7V for example.

So SYNC is taken low, then 24 bits are clocked in, then SYNC is taken high again. After SYNC is taken high, I would assume the adressed DAC output goes from 6.7V to -5.85V immediately.

But it doesn't happen this way. The DAC output is still 6.7V. If I send another 24-bit, say NOP (control register), or LOAD (control register), or another DAC value (say 3.3V), then the output is set -5.85V.


Here are some example cases or what I'm observing :

[DAC output is 6.7V]   -->  [Set DAC output to -5.85V through SPI (SYNC goes low, 24 bits clocked out, then SYNC goes high)]  --> [Output is still 6.7V]

[DAC output is 6.7V]   -->  [Set DAC output to -5.85V through SPI (SYNC goes low, 24 bits clocked out, then SYNC goes high)]  --> [Send NOP through SPI (SYNC goes low, 24 bits clocked out, SYNC goes high] --> [Output is now -5.85V]

[DAC output is 6.7V]   -->  [Set DAC output to -5.85V through SPI]  --> [Output is still 6.7V]  --> [Set DAC output to 2.5V through SPI] ---> [Output has changed to -5.85V] --> [Send NOP through SPI] --> [Output has changed to 2.5V]


TL;DR I have to send another 24-bit of data for the DAC output to take the desired voltage sent in the previous 24-bit data. If I send continuous voltage data, that means the output is always one value behind the latest value sent through SPI.


My question : Is this normal? Datasheet seems to say when LDAC is tied low while in a transfer, that SYNC rising edge sets the output. Or am I missing something?

Is it because LDAC is hardwired to low that I observe this behavior? Upon checking communications through a Salae logic analyzer, I see no problem at all in the communication itself : timings are respected, and the correct values are sent through SPI).