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SPI Input Shift Register Extra Bits Before LATCH

Category: Datasheet/Specs
Product Number: AD5412

What's up Analog Devices,

The AD5412 data sheet claims the SPI input shift register requires exactly 24 bits before the LATCH strobe to get a current output to appear.  The data sheet also claims if 25 bits are written (one bit extra) the data written will be "invalid".  Did they perhaps mean the input shift register would take the most recent 24 of the 25 bits before the LATCH and then output a current based on those most recent 24 bits?  This assumes the most recent 24 bits themselves conform to the correct format required by the AD5412.

  • Hi  ,

    As a summary of what the datasheet suggests:

    Input Shift Register:

    • 24 bits wide, accepting data MSB first.
    • Continuously clocked in on the rising edge of SCLK.
    • Contains 8 address bits and 16 data bits (Table 8)

    Latch Operation:

    • Unconditionally latches the 24 bits present in the register on the rising edge of the LATCH pin.
    • Regardless of LATCH state, data continues to be clocked in.

    Valid Data:

    • Requires exactly 24 rising SCLK edges before LATCH goes high.
    • Violating this condition (either less or more than 24 edges) invalidates the data.

    Consequences of Invalid Data: The datasheet doesn't explicitly state the exact behavior with invalid data. It could:

    • Lead to the DAC rejecting the entire data sequence and not generating any output.
    • Cause the DAC to use only the first 24 bits, potentially resulting in unexpected behavior or inaccurate output.

    Therefore it is recommended to send 24 bits precisely for reliable and predictable operation. Exceeding or falling short of 24 bits can lead to unpredictable behavior due to invalid data.

    Best Regards,

    Den

  • What's up Den,

    Thank you for your response.  I should be more clear in what my concern is.  It is not a deliberate extra clocked bit, but rather extraneous noise causing the extra clocked bit.  Please consider this example scenario:

    t=0 the AD5412 input shift register is idle, waiting for SPI input.

    t=1msec a noise transient appears on SCLK causing the input shift register to clock in one bit, suppose a logic one.

    t=2msec all is quiet.

    t=3msec the microcontroller sends a proper 24 bit data to the AD5412 which is clocked into the shift register.  LATCH is strobed upon completion.

    At this point does the AD5412 output a current in response to the most recent 24 bit data, or does it enter the aforementioned invalid state, requiring a power cycle for correction and restart?  Your comment about continuous clocking suggests the AD5412 would function correctly, with the initial errant bit clocked completely out of the shift register, then replaced with the correct 24 bits.  However the data sheet comment suggesting 25 bits is invalid goes against this.

    Sorry to be so anal about this problem but I must be sure AD5412 will work in practical situations.

    MikeN

  • Hi  ,

    The SPI lines (SCLK and SDIN) have inherent noise immunity due to required low/high times for SCLK (indicated at t2 and t3 on the timing diagram) and setup/hold times for SDIN (indicated as t6 and t7 on the timing diagram).These timing specifications act as safeguards against sudden extraneous noise, sparks, or spurs that might otherwise result in an additional clock bit. The established timing parameters help mitigate such interference, reducing the risk of data invalidation as outlined in the datasheet.

    For the best reliability and to make sure everything works smoothly, sticking to the 24-bit requirement and timing for LATCH (indicated on the timing diagram, high and low time requirement) is crucial. Also, considering ways to reduce noise in your setup can add an extra layer of protection.

    Best Regards,

    Den