AD5062 MUPS?

Question

Hi, 
 In my application I want to run the AD5062 with 1MUPS. 
 According to the timing specification in the datasheet, SCLK can be as high as 30MHz and while maintaining the other timing requirements imposed by the datasheet, I can send new code to the DAC every 1us. However, the DAC output is updated every second code only. 
 Is there further limits regarding the MUPS? I've observed that when increasing the nSYNC high time (t8 in the datasheet, page 5) to around 230ns, the DAC then updates its output on every code update, however this slows down the update rate to less than 1MUPS. 
 What is the specification on MUPS of AD5062?

EZAutoReply · Accepted Answer

Hi SDRdev22 
 You could take a similar approach to these threads below. (+) what is the maximum analog output frequency of AD5791? - Q&A - Precision DACs - EngineerZone (+) Precision DAC sample rate - Q&A - Precision DACs - EngineerZone (analog.com) 
 TL;DR We don't normally give update rate specs for precision DACs but the general formula that can be followed is Interface time + settling time . Even if you can send commands to the part, that doesn't mean it gets immediately reflected at the output of the DAC. A large part of the update rate is being covered by the settling time but that can be adjusted on a case-case basis. The spec in the ds is given for a step of 1/4 to 3/4 step. 
 Best regards, 
 Ian)

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AD5062 MUPS?