We are using the AD5541AB with a data rate of 769 kHz, VDD=2.5V, AVDD=3.3V, and external reference=2.5V. Our application is counting upward through the codes (typically from ~16000 - ~33000), with twelve samples in succession for each code. We have noticed a small spurious signal in the output at a frequency that could be caused by a cycle in DNL / INL every four code values, but within the specifications for the device. I see in the plot of typical INL versus code in the data sheet that there are obvious cycles in INL every 2048 code values. Can we expect to see patterns like that at the level of every four code values as I have described? Do you have any more detailed plots of your DNL / INL measurements?