Category: Hardware
Product Number: AD5721
Hello,
a falling edge at the CLEAR input sets the DAC register to zero-scale, midscale, or full-scale code (user selectable) and updates the DAC output. The output remains at the clear value when the CLEAR signal is returned high.
What happens when a new value is loaded into the DAC register during active (low) CLEAR Signal? Remains the output at the clear value or is the output updated to the new value? Is the CLEAR signal falling edge active or
low active?
Many thanks in advance.
Alexander
