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AD5669R - Read operation is unclear and Datasheet typos

Category: Datasheet/Specs
Product Number: ad5669R

There are a couple of mistakes in the datasheet Rev. F

The description of the read operation:

  1. I assume there is missing some explanation about the read operation which says:

The question arising from this description is how does the AD5669R know which registers to read and send to the host if there is only given one address byte which only identify the device?

I assume the mistake is that the second byte is sent from the host to ad5669 with register selection information  and not as described above. If this is true then the figure annotation of the acknowledge of the second byte is incorrect on page 23 figure 52. clock cycle 9+9=18 incorrectly states ack by master must be ack by AD56...

I hope someone can clarify this.

Finally a minor thing:

Page 26, 27, and 28

The serial shift register is 24bit not 32bit: Page 26 table 11. Page 27 table 13 and 14. Page 28 table 17 incorrectly states that it is 32 bit.



clarifications and typo
[edited by: larsen at 9:42 PM (GMT -5) on 6 Mar 2023]

Top Replies

  • Hi   ,

    Thank you for your query. A typical I2C transaction consists of three parts: 1) a slave address byte, 2) a command byte, and 3) N data bytes depending on the device. When reading back data,…

Parents
  • Hi   ,

    Thank you for your query. A typical I2C transaction consists of three parts: 1) a slave address byte, 2) a command byte, and 3) N data bytes depending on the device. When reading back data, the command byte specifies the register address to be read. The datasheet follows a slightly different format for the I2C transaction description, but this does not affect the functionality or performance of the device.

    There is a minor discrepancy in the figure 52 on page 23, where the second byte is acknowledged by AD5669R, not by the master. We also appreciate your feedback on the serial shift register size. It is 24-bit, not 32-bit as stated in some tables on pages 26-28. We will update this in the next revision of the document for clarity. Thank you for your interest and support.

    I hope this helps.

    Best Regards,

    Den

Reply
  • Hi   ,

    Thank you for your query. A typical I2C transaction consists of three parts: 1) a slave address byte, 2) a command byte, and 3) N data bytes depending on the device. When reading back data, the command byte specifies the register address to be read. The datasheet follows a slightly different format for the I2C transaction description, but this does not affect the functionality or performance of the device.

    There is a minor discrepancy in the figure 52 on page 23, where the second byte is acknowledged by AD5669R, not by the master. We also appreciate your feedback on the serial shift register size. It is 24-bit, not 32-bit as stated in some tables on pages 26-28. We will update this in the next revision of the document for clarity. Thank you for your interest and support.

    I hope this helps.

    Best Regards,

    Den

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