In our application we would like to chain several AD5554's together and run the chain at 20 MHz.
While reading through the datasheet we noticed that propagation on the SDO pin occurs on the positive edge of SCLK, the same edge use for sampling SDI. The propagation time ranges from 2 to 20 ns while the SDI data hold time is 20 ns.
This would suggest that if we directly connect two AD5554's in the chain then we will see hold time violations in all but the most extreme corners of SDO propogation delay. If we attempt to use board traces to produce the delay required to meet the hold time in the worst case (18 ns extra delay) we would need approximately 18 feet of board trace which is unrealistic. An active delay device could be used instead but this increases the number of BOM items.
I was assuming the chaining functionality would be more straightforward, otherwise the device could have been designed to update SDO on the falling edge like a traditional SPI device to avoid a costly external solution to this issue. Am I misinterpreting the datasheet?
Thanks!
