Hello,
I'm on a project that uses an AD5121 which is responsible for attenuating a 1Vpp 0.1-50Hz signal with no DC offset, but I'm failing to do any kind of communication with the chip.
Due to the fact that I'm dealing with positive and negative signal and some other constrains, I need to use a +/- 2.5v power supply on the analog part but a +3.3v power supply on the digital part, both with the same ground. According to the datasheet, I'm right where I should be to use the AD5121 in dual rail mode. And I can indeed see that it powers up correctly because the signal is half the input signal which according to the datasheet is correct behaviour.
I wanted to avoid using I2C because I already have SPI running to an AD9833 and I didn't want to level-shift I2C so I wired the DigiPot in SPI mode.
The datasheet says that VLogic should be between 1.8 and VDD (2.5v for me) so I used a 20k/10k divider to reduce the 3.3v to 2.2v which if I read correctly is in the margins of the AD5121.
Here is how the chip is connected, the 3 labels go directly to an RP2040, TP24 is connected to my logic analyser, AGND=DGND
As far as I can tell, the chip is soldered correctly and I've already replaced it once
To test things out I'm using a circuit python script. The datasheet of the AD5121 is a bit confusing as it mention both CPOL=1 CPHA=0 and CPOL=0 CPHA=1 so I tested both but no luck.
Here is my test code:
import busio
import board
import digitalio
from adafruit_bus_device.spi_device import SPIDevice
spi = busio.SPI(clock=board.GP2, MOSI=board.GP3, MISO=board.GP4)
csDDS = digitalio.DigitalInOut(board.GP6)
csRES = digitalio.DigitalInOut(board.GP7)
deviceDDS = SPIDevice(spi, csDDS, baudrate=50000, polarity=1, phase=0)
deviceRES = SPIDevice(spi, csRES, baudrate=50000, polarity=1, phase=0)
with deviceRES:
spi.write(bytes([ 0b00010000, 100 ]))
with deviceRES:
spi.write(bytes([ 0b00110000, 0b00000011, ]))
with deviceRES:
spi.write(bytes([ 0b00000000, 0b00000000, ]))
I have a logic analyser hooked up and I can see that valid data seems to be transferred but I'm not getting a response from the AD5121, nor am I seeing the analog signal change
The first SYNC high is 94us long and the second is 51us.
There is a minimum pause of 100us before the first clock pulse after the SYNC low
I'm a bit lost here, I can not see what is wrong especially since power works the chip goes to the default state and I can see the signal!
Is there a "power-up" command I should send in order for the chip to accept other ones? Have I messed up the wiring?
Any help would be appreciated here.
Thanks,
Samuel
Hi,
Yes, I forgot to mention it, but a 5.1k (all I had on hand, is it an issue?) pull-up is present on SDO.
Here are screenshots of the waveform of SCK set to 5kHz. I don't have the best oscilloscope at hand, but I think this looks fine.
500mV @ 500us
500mV @ 100us
At 50kHz the waveform isn't the best (but still usable I would think). I don't need speed at all, so 5kHz is fine. Someone I know recommended a diode with a pull-up, I might try that at some point to get a cleaner signal that spot on 2.5v
I tried the double 0x1064 (CPOL=1 CPHA=1) here is the full logic analyzer capture, the turquoise line is when I started the script and the red is the trigger:
Double 0x1064 should result in the first one being shifted out at the beginning of the second one, right? If yes, is there anything that could disable the shift register?
I've also tried to set the scope to trigger on the rising/falling edge of SDO to see if maybe it was my logic analyzer, but it didn't trigger at all.
I've had this question on my mind I checked it already but, would the chip power up with GND or VLogic missing and still go to the default position but ignore inputs?
Thanks for your response,
Samuel
Hi,
Firstly, I need to apologize, the logic analyzer SPI stack decoder was using the wrong MISO pin, it now shows the correct 0xFF from the pull-up. I should have realized sooner
As for the sync, the screenshot doesn't help, but it actually goes high 12us later than the last clock low. I added a delay anyway to verify, but it didn't change anything
Here is a capture of 0x1064 twice then x3003 then x0000
And here is one of 0x1064 twice, then x0000
I spoke with someone I know, and we ruled out the VCC / VSS / GND / VLogic pins because a defect in either of these pins would be reflected in the signal.
The current theory is that something is wrong with either DIS, SCK, SDI or SYNC#.
There's also WP#, RESET#, INDEP, LRDAC# but I think that these pins wouldn't cause the daisy-chaining to stop working.
The issue is that if I probe directly at the pad, I get the signal from the MCU, meaning there isn't a break/short/bridge between the resistors and AD5121 and that it's probably solder correctly.
I was wondering if the 2.2v is actually sufficient at VLogic=2.5V The datasheet says it's fine (2.2 > 0.8*2.5) but it'as a small margin.
How likely is it that the two chip I got are dead?
Anyway, thanks for your help, I would appreciate if you have any other ideas!
Samuel,
Hi,
No, the device does not respond at all, no change when writing to RDAC, no daisy-chaining.
Here is SCLK and SDI on the scope and the corresponding logic analyzer capture
Here is the complete analog part of the schematic:
And a part of the digital side
Kindly let me know if you need more.
Thanks for your help.
