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AD5686R Output voltages are not as expected

Category: Software
Product Number: 505-EVALAD5686RSD Z-ND
Software Version: NA

Using EVALAD5686R with ADuCM363 micro controller in SPI mode, with 2.5 reference voltage.
DAC converted voltages are not as expected in few data point. Could you please suggest what might be going wrong?
Below are the data

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  • HI, 

    What SPI Mode are you using? I believe it should be SPI Mode 1 or 2 for the AD5686R. Also, check your logic levels vs the logic supply on the chip. An SCLK, MOSI, and SYNC osc capture on the failing values would be best.

    Regards,

    ~Ian

  • Hi Ian,

    we have tried on SPI Mode 0,1 and 2.

    Above is the oscilloscope data, for the data 0x6FFF, DAC output voltage suppose to be 1.094, but output voltage is zero. please 0x7FFF DAC out voltage is as expected.

    Above oscilloscope data has

    Command: WRITE_AND_UPDATE_CMD (0x3)

    Address: DAC_A (0x1)

    Data: 0x6FFF

    Could you please suggest, what might be going wrong?

  • Hi, 

    Sorry, I didn't see the /SYNC signal on your scope shot. What I'm seeing now is that there are more than 24 clocks on the bus, and apologies as I don't have an eval board on hand, but I'm not sure it would create a valid response from the DAC in this case. 

    Could you try to get the /SYNC waveform and send only 24bits word to the DAC? SPI Mode 1 or 2 should work, with the data valid at the CLK falling edge. 

    Regards,

    Ian

Reply
  • Hi, 

    Sorry, I didn't see the /SYNC signal on your scope shot. What I'm seeing now is that there are more than 24 clocks on the bus, and apologies as I don't have an eval board on hand, but I'm not sure it would create a valid response from the DAC in this case. 

    Could you try to get the /SYNC waveform and send only 24bits word to the DAC? SPI Mode 1 or 2 should work, with the data valid at the CLK falling edge. 

    Regards,

    Ian

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