Ad5761R trouble getting output voltage to be consistent

Hi, 

Can you give a zoomed-in scope shot of your SCL, SDI, and CS signals? users often times get this mistake, the data should be sampled at the clock falling edge. 

LarkinM said:

The dac should be starting up in 5v by default and does on the bare board. I have also attached a screenshot of the schematic, as well as scope plots. 

This statement isn't clear for me. Do you mean here the output or the supply of AD5761R is at 5V at start-up?

~ian

Hi, 

Can you give a zoomed-in scope shot of your SCL, SDI, and CS signals? users often times get this mistake, the data should be sampled at the clock falling edge. 

LarkinM said:

The dac should be starting up in 5v by default and does on the bare board. I have also attached a screenshot of the schematic, as well as scope plots. 

This statement isn't clear for me. Do you mean here the output or the supply of AD5761R is at 5V at start-up?

~ian

I meant to say the output should be 5V at start-up based on the software being sent. 

The solution was the CLK line was overshooting bcs of filtering on other spi devices on the bus. I added a resistor in series with CLK line at the microcontroller output and it fixed the issue. There are also different rise times for the output on the STM32 and I'm looking into changing those. 

Good to know that the error was fixed. I find it usefull to add those series resistors, ~22ohm, on serial interface lines when I do board design. Especially in your case where there are plenty of other devices on the bus. 

If you have any other queries on our DACs don't hesitate to put it up here on our forums. 

Regards,

~ian