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DAC configuration register to control DAC channel

Category: Datasheet/Specs
Product Number: AD5380

Hi,

I would like to interface  AD5380 EVM Module with STM32 using I2C or parallel communication. 

Is there any example source or driver is available for this? 

I lookout for datasheet and other resources but not able to find it. 

I am not able to find register details for DAC  to configure and control individual channel.

There is parallel and serial mode are available , but no document found to test this mode individual.  

I need specific register details and communication steps so that I can communicate with DAC with parallel and serial (I2C) .  

Any help would be appreciable. 

Thanks & Regards,

Ashvin Makwana 

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  • Hi,

    Thanks for your response.

    I have configured the DAC into serial I2C mode by setting jumpers and I have verify the I2C communication with MCU , by getting Device address. 

    I am exploring datasheet regarding register read/write frame structure, it bit confusing to understand. 

    I have checked that driver but I am not aware about Linux, so it is more complicated for me to understand that driver.

    if possible can you help to send frame structure for I2C communication and register address for configure  and controlling DAC.

    Thanks & Regards,

    Ashvin Makwana

  • Hi,

    I have already check the datasheet and try to communicate with DAC but i am not getting any data. 

    In datasheet no specific example are provided for I2C read and write operation. Datasheet provide only 4 ,3 ,2 byte I2C write Waveform diagram only. 

    No clear data found in datasheet to operate I2C communication.

    1. I am trying to measure data on DAC channel 0 and other but not getting anything on it.
    2. How to select I2C communication Mode 4 byte, 3byte or 2byte?
    3. I tried Soft Reset & Power up sequence 1st and then set DAC channel.
    4. How to select DAC channel ?
    5. Read Data form DAC control register?  
  • Hi Ashvin


    1. Please check the Address byte in figure 31 of the datasheet. The bits AD1 and AD0 are appended to the end of the address byte. If you see table 2 of the eval board user guide (EVAL-AD5380SDZ/EVAL-AD5382SDZ (Rev. A) (analog.com)) you will see LK12 and LK11 links that control these two bits. By default, they are both tied to ground, so the address is 0x56 (unless you have changed them)


    2. Figures 31, 32 and 33 outline the differences between 4-byte, 3-byte and 2-byte modes of communication. 4-byte communication is when the host sends a STOP condition (pulling SDA high before positive edge of last SCLK transition) after 4 bytes of operation. If the SDA line remains low, the device understands that the next channel is to be updated, and expects only 3 bytes. 2-byte mode is when you send an all 1s pointer byte, and the internal channel pointer auto increments as long as the STOP condition is not sent.


    3. Again, please check above two points first.

    4. DAC channel is selected by the pointer byte. Figures 31 and 32 indicate where the pointer byte should be, and the encoding scheme is given in Table 16 in the datasheet.

    5. Readback is given in figure 30.

    Regards
    Suraj