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AD5663 output with large spur

the input clk period = sclk =40Mhz

the timing set as the pic upside, and I set the input data rate synchronized with the DAC output as 40M/253clk=158.1Khz,

the verilog code is as below

//clk_in ==  40Mhz
module AD5663R(
	input clk_in,
	input [15:0] data1, data2,
	output reg clr = 1, sync=0,  dout=0,
	output sclk,
	output reg en_sck=0,
	output reg send_en = 0,
	output reg sample = 0
    );

	reg [15:0] data01 = 0, data02 = 0;
	wire [23:0] cmd_ref, cmd_data01, cmd_data02;
	assign cmd_ref = 24'b00_111_000_000000000000000_1; // set vol reference
	assign cmd_data01 = {8'b10_000_000, data1}; // channell
	assign cmd_data02 = {8'b01_000_001, data2}; // channel2
	assign sclk=en_sck?clk_in:1'b0;	
	reg [7:0] cnt = 0;
	reg [23:0] cmd = 0;	
	reg [5:0] state = 0;
	always @(posedge clk_in)
		begin
		if (cnt>=254-1)
			begin
			sample<=1;
			cnt<=0;
			sync <= 0;
			en_sck<=1'b0;
			end
			
		else if (cnt>=54-1)
			begin
			cnt<=cnt+1;
			sample<=0;
			send_en <=0;
			en_sck<=1'b0;
			sync <= 1;
			end
			
		else
			begin
			cnt<=cnt+1;
			sample<=0;
			send_en <=1;
				case(state)			
				6'd0:
					begin
					state <= 1;	
					en_sck<=1'b0;
					if(cmd == 0)
							cmd <= cmd_ref;
						else if(cmd == cmd_data01)
							cmd <= cmd_data02;
						else
							cmd <= cmd_data01;
						
					end
				6'd1: begin state <= 2;	sync <= 0; end				
				6'd2: begin en_sck<=1'b1;state <= 3; dout <= cmd[23]; end
				6'd3: begin state <= 4; dout <= cmd[22]; end
				6'd4: begin state <= 5; dout <= cmd[21]; end
				6'd5: begin state <= 6; dout <= cmd[20]; end
				6'd6: begin state <= 7; dout <= cmd[19]; end
				6'd7: begin state <= 8; dout <= cmd[18]; end
				6'd8: begin state <= 9; dout <= cmd[17]; end
				6'd9: begin state <= 10; dout <= cmd[16]; end
				6'd10: begin state <= 11; dout <= cmd[15];end
				6'd11: begin state <= 12; dout <= cmd[14]; end
				6'd12: begin state <= 13; dout <= cmd[13]; end
				6'd13: begin state <= 14; dout <= cmd[12]; end
				6'd14: begin state <= 15; dout <= cmd[11]; end
				6'd15: begin state <= 16; dout <= cmd[10]; end
				6'd16: begin state <= 17; dout <= cmd[9]; end
				6'd17: begin state <= 18; dout <= cmd[8]; end
				6'd18: begin state <= 19; dout <= cmd[7]; end
				6'd19: begin state <= 20; dout <= cmd[6]; end
				6'd20: begin state <= 21; dout <= cmd[5]; end
				6'd21: begin state <= 22; dout <= cmd[4]; end
				6'd22: begin state <= 23; dout <= cmd[3]; end
				6'd23: begin state <= 24; dout <= cmd[2]; end
				6'd24: begin state <= 25; dout <= cmd[1]; end			
				6'd25: begin 
						 state <= 26; 
						 dout <= cmd[0]; 
						 
							if((cmd==cmd_data02) || (cmd==cmd_ref))
								begin
								send_en <= 0;
								end
							else							
								send_en <= 1;
						 end
				6'd26: begin 
						 state <= 0;
						 sync <= 1;
						 end
				default: begin state <= 0; end
				endcase
			end

end					
endmodule

however, when output a 100Hz sine wave, the spur is so large, the yellow wave is filtered by RC circuit,the green wave is unfiltered directly output from DAC AD5663

can you help me point out the problem please?

  • The glitches seem to be aligned with the samples, but the D/A conversion glitch must below 15 mV. Perhaps there is a misalignment of the bits that produces a corrupted waveform. I suggest testing with a ramp to ensure that codes are latched in correctly.

  • Really appreciate for your answer ,dear sir!

    Firstly , it did seem like the timing at sampling ,but why it just happened at some sampling points and the main wave was still right?

    Another question is :

    What if the sclk have some delay so that the reading haven't finished in 24 clks, and then the sync is pulled up, what will happen to the output? 

    is it just lost several LSBs and the output still keep almost right? 

  • You could have a signal integrity problem (crosstalk or reflections) that cause the rising edge of SPI signals to move depending on the bits being serialized.

    Registers cannot be partially written. If SYNC rises before the 24th clock edge, data is ignored. If this happens, you can have missing codes in the waveform but this would not cause a glitch.