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AD5541 max output rate


I have a question regarding the AD5541 maximum output value update.

As far as I understand the main limiting parameters is the settling time.

but I am not able to understand if the SPI interface is a bottleneck or not.

In the datsheet is reported that you need 16 clock pulses to send one data after the CS is put low. But what happens if I want to send data continuosly? Can I keep sending the data on DIN line and so to obtain 2 different output values I just need to wait 32 clock pulses?   

And what happens if I have more than one AD5541 connected to the same SPI interface?  

Thanks in advance

  • Hi, 

    One SPI Frame running at the maximum clock (25MHz) should be (t12+t4+15*t1+t7) ~= 0.66us while settling time is at 1us. with the SPI interface time shorter than the settling time, you can have a maximum update rate at the output which is entirely dependent on the settling time. 1/1us = 1MHz. You can time it so that .34us after the first frame, you can send you 2nd frame so that right after the output settles to the output set by the first frame, it can start to change for the output set by the 2nd frame, and so forth. 

    Of course, if you're using slower clock rates, your SPI frame would exceed the settling time and be the bottleneck. 

    In the case of having multiple AD5541 on the same SPI interface, if you prefer to control each one separately, you must have individual control on the /CS pins per device. 

    Best regards,


  • Hi iandal,

    thanks a lot for your kind help.

    So I have to pull the /CS HIGH and then LOW between each samples? Even if I want the DAC to output the same value..Do you confirm this?

    Best regards

  • Hi, 

    Yes. Data can be loaded to the part only while CS is low and the CS low to high transition transfers the shift registers content into the DAC register. 

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