LTC2654 Latency difference

LDAC should be pulled high.  What is the trigger that is capturing this data?  You are correct they latency shouldn't this long, it should be like channel A, within a few micro seconds.  Are the B/C/D channels collected at the same time as channel A?

LDAC should be pulled high.  What is the trigger that is capturing this data?  You are correct they latency shouldn't this long, it should be like channel A, within a few micro seconds.  Are the B/C/D channels collected at the same time as channel A?

Hi

Thank you for your reply.

Please see following picture which shows the B/C/D channels triggering Channel A with LDAC=H fix.

Our customer took the following picture the voltage swing between 0x0000 and 0x07FF at their lab.

DAC C delay 20us from DAC A.

Our customer found as the voltage swing decreases, the latency increases.

Our customer sent their DC1678A-A to our lab.

I confirmed our customer’s DC1678A-A at our lab.

LTC2654 was wrote by following command step.

1.0x2F0000 (write 0x0000 to all input registers and update all DAC registers )

2.Offset period “A”

3.0x2F01FF (write 0x01FF to all input registers and update all DAC registers )

4.Offset period “B”

The following 3 pictures show the latency differences between Offset period “A”=610us, 142us and 10us triggering CS rising edge.

DAC C latency is 60us at Offset period “A”=610us, 17us at Offset period “A”=142us and 10us at Offset period “A”=10us .

As Offset period “A”= increases, the latency increases.

Is  this latency delay normal ?

Could you confirm ADI lab using DC1678A-A ?

I also found latency of VCC voltage dependency.

Next picture shows the latency at Offset period “A”=610us VCC=3V.

DAC C latency is 60us at VCC=5V and 43us at VCC=3V. As VCC voltage increases, the latency increases.

Best regards

N.Kokubo