Hi, I would like to use the AD5686R (in combination with an FPGA) to generate 4 channels, each channel with an sample rate of 500KS/s.
The SPI timing seems to suggest this is possible. At 50 MHz it takes 25 cycles (24 bits + 1 for the SYNC pulse) to send 1 data word, so that would be exactly 2MS/s for the 4 channels.
(if we run into issues with timing we could run the DAC at 45MHz and 450KS/s, but we prefer to do 500KS/s).
However, the timing diagram also says there is a minimum time between SYNC rising edges of 830ns (t9), with a note saying it means DAC register updates.
Does this mean:  I cannot update any channel at a rate faster than 830ns (which would mean I cannot reach an total update rate near 2MS/s),
or  does this mean I cannot update the same channel faster than 830ns (which would mean as long as I write and update different channels every frame I could reach my target sample rate)?
Thank you for your help!