AD5686 Vlogic level and GAIN pin

Hello,

I am looking at the datasheet of the AD5686/AD5684 (revision C) and there are two somewhat unclear topics I was hoping someone could help me with.

1. Vlogic level in relation to Vdd:

On page 6, note 1 says that the SPI speed of 50MHz is only valid if Vdd is between 2.7V and 5.5V and while Vlogic is between 1.62V and Vdd.

Does this note somehow imply a voltage sequencing requirement? So should Vdd also be higher than Vlogic during startup?

What would be the effect on the SPI speed if Vdd is less than Vlogic?

Is it okay for the IC if Vlogic is already active (1.8V) with some logic levels (high and low) on the digital input pins, before Vdd starts up and reaches its final value?

(On the same page at the top of the timing characteristics table it says, that Vdd should be between 2.7V and 5.5V and Vlogic should be between 1.62V to 5.5V.)

2. GAIN pin voltage level inconsistency in datasheet:

On page 10 in the table the GAIN pins seems to be related" to Vlogic.

On page 18 in the description it seems to be related to Vdd.

I know it is related to Vlogic, since there was already a topic about this, but it would be nice if the datasheet would be consistent.

https://ez.analog.com/data_converters/precision_dacs/f/q-a/27557/ad5686r-ad5685r-ad5684r

Thank you!

  • 0
    •  Analog Employees 
    •  Super User 
    on Sep 24, 2021 7:07 AM

    Hi, 

    The normal supply sequencing should be VDD (device supply) then Vlogic. Normally, if it wasn't clearly stated in the d/s, this sequence can be overlooked and it should be fine. and the logic pins are referenced to Vlogic, so it should be safe to have some digital levels at startup on the pins. 

    As mentioned in the d/s, the max spi clock is at those conditions. Outside of it, we couldn't guarantee the performance. This means that this most likely wasn't covered during the device testing. 

    Thanks for pointing out the gain pin typo. we'll include this on the future revisions of the d/s.

    let me know if you have further questions

    Best regards,

    Ian

  • Hi Ian,

    thank you very much for the answer!

    I did not find anything power up sequence related in the datasheet except the one note regarding the SPI clock speed testing conditions and there was nothing listed regarding this in the normal operating conditions or the absolute maximum ratings of the device. Based on this and your feedback too I will not implement any specific power sequencing for these two power supplies.

    Just to be on the safe side, can you please confirm, that every pin of the device is a logic level pin, except if it is a power pin or analog output? (So pins SDO, LDAC, GAIN, SCLK, SYNC, SDIN, RESET and RSTSEL would be logic level pins. For LDAC, RSTSEL and GAIN this is explicitly described in the datasheet. The specifications of SDO are linked to Vlogic. The other pins are connected to a processor on figure 43 and 44. )

    Best regards,

    Gergely

  • 0
    •  Analog Employees 
    •  Super User 
    on Sep 28, 2021 1:22 AM in reply to gdzsudzsak

    Hi, 

    (So pins SDO, LDAC, GAIN, SCLK, SYNC, SDIN, RESET and RSTSEL would be logic level pins.

    This is correct. One thing you could do to check this is to do a diode check using a multimeter. connect the ground lead to VLogic and the Voltage Lead to the pins, if a diode voltage is seen then that pin is logic level. It is quite normal for logic pins to have protection diodes tied to their reference supply. 

    Best regards,

    Ian