I am looking at the datasheet of the AD5686/AD5684 (revision C) and there are two somewhat unclear topics I was hoping someone could help me with.
1. Vlogic level in relation to Vdd:
On page 6, note 1 says that the SPI speed of 50MHz is only valid if Vdd is between 2.7V and 5.5V and while Vlogic is between 1.62V and Vdd.
Does this note somehow imply a voltage sequencing requirement? So should Vdd also be higher than Vlogic during startup?
What would be the effect on the SPI speed if Vdd is less than Vlogic?
Is it okay for the IC if Vlogic is already active (1.8V) with some logic levels (high and low) on the digital input pins, before Vdd starts up and reaches its final value?
(On the same page at the top of the timing characteristics table it says, that Vdd should be between 2.7V and 5.5V and Vlogic should be between 1.62V to 5.5V.)
2. GAIN pin voltage level inconsistency in datasheet:
On page 10 in the table the GAIN pins seems to be related" to Vlogic.
On page 18 in the description it seems to be related to Vdd.
I know it is related to Vlogic, since there was already a topic about this, but it would be nice if the datasheet would be consistent.