How to disable CRC for SPI in AD5758 ?
The register available to disable CRC (register 0x10, DIGITAL_DIAG_CONFIG, bit 0 SPI_CRC_EN) requires a CRC to use it.
The command to disable CRC is 0x10005C31. 0x10005C sets bit 0 to 0 while the rest is not changed. and 0x31 is the CRC8 code for 0x10005C. This means you still need to write 32-bits data for the disable command, and after that, you could use 24 bits data write/read.
can this be done right after calibration memory refresh ? or must it be done later, say after all required startup register setups ?
also, slip-AD1-AD0 (0-1-0) must be in the 1st byte to disable, correct:
testA_pTxData = 0x50;//Address: 0x10, 010 1 0000
Wondering why you have 0x5B assigned to TxData here and not 0x86? 0x86 is the correct CRC. (testA_pTxData = 0x5B; //0000 => 0x86;) , like wise for testA_pTxData = 0xA1; //00=> 0x6B;.
I would suggest disabling echo mode until you have the two stage readback working correctly.
I assume the AD1 pin on your board is tied to a logic high? e.g. > 3V?
I can't see the image I don't have access, can you port a snippet here? The AD5758 will not respond if the SPI frame is invalid so either the CRC is incorrect (see my question above on the CRC) or the frame itself is not valid i.e. clock edges etc... Can you post a snippet here instead? Also a scope capture image of the SPI frame you are sending would be good.
Can you tell me what is what in the scope plot? I assume yellow = SDI, Blue = SCLK, which one is CD and SDO? The chip select needs to be pulled high for the data to be clocked into the AD5758. Also the clock edges are supplied by the master to the AD5758, so the 2 clock bytes you see are likely an issue in your code.
For a two stage readback you need to first write what register you want to read to register 0x13 bits 4:0, then to get the data back from the 5758 (assuming the SPI frame you sent is valid) you need to bring CS low and clock in 24 bits (CRC not enabled) to clock out the data on SDO. This is the NOP command, SDI is all 0s.