EVAL-AD5700 circuit connect

Or, can I do it like the picture below? Only test the function of FPGA and check whether FPGA can connect with AD 5700 successfully. If not, can you correct me? Thank you very much!

Hi, 

This second image you sent should work fine. You can check out the following design materials for reference. 

UG-382 (Rev. A) (analog.com)

CN-0270 (Rev. B) (analog.com)

Best regards,

Ian

I encountered a problem of receiving incorrect data during loopback test.
I connect FPGA with ad5700, hart_in of ad5700 and hart_out of ad5700are connected together. UART io of FPGA and ad5700 are connected together. Set the duplex of ad5700 to B,so I want to do a loop test.
I connect the 5V VCC output of FPGA to the VCC of ad5700 and the 3.3V VCC output of FPGA to the iovcc of ad5700.
During the test, FPGA sends Hart data FF, FF, FF, FF, FF，E6, 09, 0A, 0b, 0C.... Then I want to wait for ad5700 to receive the data and send it back to FPGA. However, when my FPGA receives the data, it can only receive FF, FF, FF, FF, FF and E6 at most. Then the following data will be wrong. What's the problem?
The following figure 1 is the connection diagram of FPGA and ad5700;
Figure2 is the waveform of FPGA ILA. After receiving FF, it enters the preamble state from the idle state;
Figure3 is the waveform of FPGA ILA. After receiving E6, it enters the delimiter state from the preamble state;
But the receiving state machine of FPGA can not enter the following state, and the received data will be disordered.
Hope to get your advice!