Post Go back to editing

Noise optimized layout of ADP1032

Hi all!

The ADP1032 is recommended to power the DAC AD5758. We're in search to improve the noise of this regulator. 

There is obviously an option to split SPI Ground and Power ground for ADP1032, since these gounds have separate pins at the IC. Is it possible to improve noise of the voltage regulator of ADP1032 with splitting these gounds?

Any advice for a workaround to improve the noise for voltage rail for the ADP1032 will be welcomed!

Parents
  • Hi Dmitry,

    Thank you for using the ADP1032 and AD5758 in your application.

    I'm Jeff, the apps engineer for the ADP1032 and I need further informafion about your problem. Can you please provide more information about the noise you are trying to improve and how you configured your circuit to help me understand your problem. Do you know what frequency it might be (125khz? 250khz?, 500khz? or just random noise?). And by how much you want to improve it? Are you synchronizing the ADP1032 to AD5758 thru the SYNC/CLKOUT pin? Are you using the DPC function of the AD5758? Where do you get your SPI supply from VLDO output of the AD5758 or directly at VOUT2 of the ADP1032?

    As you know, the ADP1032 have 2 switching regulators and the AD5758 DPC is also a switching regulator that are inherently have output ripple, the flyback operates at 250khz and the buck operates at 125khz and the DPC operates at 500kHz, you can use an additional LC filter to reduce the ripple on these rails if you see these noise in the output. For the ADP1032 SPI, yes it would be better to split SPI ground from the power GND especially if you are using the VLDO of the AD5758 as the SPI supply. 

    Any further information about your problem would be great for me to understand it further and provide the best approach to solve it

    Thanks and regards,

    Jeff

  • Hi, Jeff, 

    Attached are the waveforms obtained at the output of EVAL-ADP5758SDZ evaluation board, loaded with 680Ohm resistor. The board is configured with default jumper settings,  CLKOUT switched on and fed to SYNC, VLDO powers SPI, DPC function in use. Output noise seems to be contributed mostly by fly-back regulator and has a strong component up to 200mVp-p at 250kHz repetition rate.PDF

    It's needed however to achieve noise to be less than 0.2%, i.e. about 20mV. Switched supplies and DPC function are unavoidable because of the project’ power and space constraints.

    So what's are your suggesions for a layout to achive the best possible noise performance?

    Note that the ADP1031 was finally selected. 

  • Hi Dymitry,

    Thank you for providing the scopeshots, yes I agree that the spikes aligned to the Flyback regulator operating frequency. May I know how you measured these scopeshots? Are you using the default voltage probe with the long ground clip? The long ground clip creates a long ground loop (plus additional inductance) that can pick up external noise thus worsening the spikes/ringing. I would suggest you try the tip and barrel method probed across the output capacitor - this minimize the ground loop. Here is an app note comparing the tip and barrel method vs the long ground loop measurement for reference.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN-1144.pdf

    Let me know what you got using this method.

    Thanks and regards,

    Jefferson

  • Hi, Jeff, definetly the tip and barrel method was used and the ground return loop was minimized. 

Reply Children