Digital Potentiometer AD5142 datasheet calls out an edge rate of 1ns/V in note 1 under (Interface Timing Specifications) in reference to the input signal used in test. Is there an edge rate or rise/fall time requirement for the SCLK pin?
Digital Potentiometer AD5142 datasheet calls out an edge rate of 1ns/V in note 1 under (Interface Timing Specifications) in reference to the input signal used in test. Is there an edge rate or rise/fall time requirement for the SCLK pin?