Digital Potentiometer AD5142 datasheet calls out an edge rate of 1ns/V in note 1 under (Interface Timing Specifications) in reference to the input signal used in test. Is there an edge rate or rise/fall time requirement for the SCLK pin?
Edge rate of 1nS applies to all digital input signals which include SCLK.
Someone is currently looking into this query.
So is 1ns/V the suggested/required edge rate or just what was used in test to get the specifications seen in the datasheet? -Thanks
The edge rate of 1ns/V is used to get the timing specifications mentioned in the DS.
Is there a maximum edge rate then?
There is no maximum edge rate specified. All the timing specifications are given with respect to certain conditions like edge rate, voltage levels, capacitive loads. supply and temperature conditions.
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