AD5593R VLogic and VDD range dependency is not clear in the datasheet.


VLogic range is stated "1.8V to VDD" in the Power Requirements section but it is stated "1.8V to 5.5V" in other places and "-0.3V to 7V" in the Absolute Maximum Ratings.

Is it really VLogic must be lower voltage than VDD?

What I really want to ask is;

When the VLogic is continuously 5V and VDD (VDD is normally 5V) is disconnected, will the chip be damaged or is it safe?

If it is safe what will be the DAC output pin status?  Hi-Z ?



  • 0
    •  Analog Employees 
    on Jan 18, 2021 5:59 AM

    VLOGIC has to be lower or equal to VDD.

    If VDD is disconnected and VLOGIC is on, all I/O pins will reset to three-state as all I/O pins operate on VDD.

    Can you provide any reason why you want to disconnect VDD while VLOGIC is powered?

  • I'm designing a board for simulating some analog sensors for a system.
    The system supplies the 5V sensor voltage. Sometimes disconnects the sensor voltage for diagnostic purpose.
    My simulator board is always on and switches the system main power, so no 5V sensor supply when the system is off.

    If I supply the VLogic with simulator board and VDD with sensor supply, It will be guaranteed DAC outputs Hi-Z when the no sensor supply.
    Otherwise I need to check the sensor supply continuously and set the all DAC outputs to Hi-Z when the sensor supply is gone.

    You said "VLOGIC has to be lower or equal to VDD.".
    This may be needed for normal operation. In my condition (VLogic=5V and No VDD) Does it damage the chip?

  • +1
    •  Analog Employees 
    on Jan 18, 2021 9:26 AM in reply to ilmete

    There is no issue with the device if VLOGIC = 5V and no VDD as long as the I/O pins are unloaded. 

    If you want to keep all DAC outputs to three-state, you can use the Power-Down register from Table 26 in DS.

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