I am using an AD5761R DAC connected to an FPGA. All signalling and signal timing to the DAC looks good and I am doing a simple test:
Signal Conditions for this test: RST, CLR and LDAC are held high in the FPGA.
SYNC, CLK and Data come from the FPGA.
Clock is normally low and running at 6.25Mhz
Write a SW Full Reset by writing 24'h0F0000
Write The control register with: 24'h040329
Which I think sets the following parameters:
CLR Voltage to mid-scale
Over rage enabled (I have tried both options on this)
Power up voltage to mid-scale
About 12us after the control register write I see the output go to mid-scale and stay there for 22us.
The output then jumps to full scale for ~10us and then goes back to 0V and stays there,
Please see the attached scope shot.
Writing to the input register or DAC register after this does not change the output.
Has anyone seen this behavior before?
Edit 12/03/2020: Fixed generic on the subject for tracking.
[edited by: iandal at 2:19 AM (GMT -5) on 3 Dec 2020]