EVAL-AD5761RSDZ

Hi,

I am currently working with the EVAL-AD5761RSDZ. I am trying to control the DAC with a Python script running on a Raspberry Pi.

As far as I know I have to write to the control register after powering up. By sending 0x04 04 11 the DAC should be configured to the output range from 0V to 10V.  Then I can use the write and update command, 0x03 ff ff, to set the voltage output to its maximum. However, the output remains unchanged at 0V. I have also tried to start with a "software full reset" command, but the result is the same. While checking the connections of the DAC I couldn't find any issues. The signal on the MOSI line goes into the chip, as well as the CLK signal, the sync signal and the provided power.

Do you have any idea what I could be doing wrong or how I can solve this problem?


Parents
  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 3, 2020 3:12 AM

    Hi, 

    Have you checked the jumper settings on the EVAL-AD761RSDZ? What's your setting for LK1 to LK4?

    How about the supply connectors J1, J2, J5? What's your voltage setting on these pins?

    Can you also show an OSC capture of your SPI transactions? 

    Are you using internal reference, external on-board reference, or external reference?

    Hope you can answer the above queries so I can helpo you out.

    Best regards,

    Ian

  • Hi,

    Yes I did checked the jumper settings, but I feel like that this is not the cause of my Problem. The Links of LK2 and LK14 are removed. On the other hand, the Links of LK7 and LK8 are inserted and the Links of LK_AVDD, LK_AVSS, LKDVCC, LK_REF, LK_VOUT+, LK_VOUT- are conected to B.

    Power is supplied via the  PVIN_3V-15V connector. The input voltage and messured voltage on these conectors is 10V.  The voltage messured on the Vss Pin is -11V and on the VDD Pin 21V. The Voltage at the DVcc Pin lays around 2.3V.

    I am using an internal reference selected by position B of the LK_REF Pins.

    This is the Date send to initilize the DAC.

    And this is the write and update command.

    The yellow signal is the clock signal and the green signal is the MOSI signal.

    I hope that this answers your questions. If not, please let me know what else you need.

    Best regards,

    Nils

  • Hi Ian,

    Thank you very much for the clarification with the VREF setup.

    I did not add the SYNC line OSC, so it is not visible in the snapshots. Before I contacted you, I checked the times listed in the data sheet and found no abnormalities.

    I feel like the master is not necessarily the reason for the behavior of the SDO line. I tested the output of the line once with the master connected to the SDO pin and once wtih the Raspberry not connected. In both cases the MISO line was set to high during SPI communication.

    In addition to that, I tested the SPI communication with an ADC and it worked without any problems.

    No, I have not tried a different master board yet. But I thought on testing the DAC with the SDP board and the included software once the SDP board arrives.

    I have a question regarding the diodes built in: What do the diodes indicate and when are they supposed to be on?

    Best regards,

    Nils

  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 19, 2020 12:09 AM in reply to Nils

    Hi Nils, 

    I have a question regarding the diodes built in: What do the diodes indicate and when are they supposed to be on?

    The diodes on the IO pins act as protection, in case a voltage higher than the +supply rail or a voltage lower than the -supply rail (or in our case, GND)  is applied to them, the diodes would turn on. 

    You could do a diode check using a DMM, (applying the +terminal to DVCC and the -terminal to the IO pins) to see if the protection diodes are still OK. You should get a ~0.7V reading. But looking back at your scope shots, I see that SDO only comes high when you start the spi transaction. 

    What are the states of the other IO pins? (/LDAC, /CLEAR, /RESET) They should be biased properly from the master and not left hanging. 

    Best regards,

    Ian

  • Hi Ian,

    The diodes on the IO pins act as protection, in case a voltage higher than the +supply rail or a voltage lower than the -supply rail (or in our case, GND)  is applied to them, the diodes would turn on.

    In that case I think this could be the problem. The diodes are an while I am supplying 10V via the PVIN connector . While operating with the current pin setup I messure around -11V at the LED_AVSS Pin and 21V at the LED_AVDD Pin. They are also on when the evalution board is connected to the SDP board.

    What are the states of the other IO pins? (/LDAC, /CLEAR, /RESET) They should be biased properly from the master and not left hanging. 

    These Pins are set to high via the Python script and the voltage messured lays around 2.8V. This is how it should be, isn't it?

    Best regards,

    Nils

  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 24, 2020 12:32 AM in reply to Nils

    Hi Nils, 

    Sorry. I think I got confused about the diode question. Were you referring to the LED_AVDD and LED_AVSS? If so, these are just indicators for the output of the onboard DCDC. Also, the diode test mentioned is for the IO pins only. 

    You could do a diode check using a DMM, (applying the +terminal to DVCC and the -terminal to the IO pins) to see if the protection diodes are still OK. You should get a ~0.7V reading.

    This above step should be +terminal to the IO pin and -terminal to the DVCC pin for diode checking using DMM. 

    What are the states of the other IO pins? (/LDAC, /CLEAR, /RESET) They should be biased properly from the master and not left hanging. 

    These Pins are set to high via the Python script and the voltage messured lays around 2.8V. This is how it should be, isn't it?

    Yes, the pins should be set high if not used but the value for it to be registered as high should be >0.7xDVcc as stated in the datasheet (Page 4, Logic Inputs VIH spec)

    Best regards,

    Ian

  • Hi Ian,

    Yes, the pins should be set high if not used but the value for it to be registered as high should be >0.7xDVcc as stated in the datasheet (Page 4, Logic Inputs VIH spec)

    This really seems to be the cause of the problem, but I also think the EVAL board is broken.

    I tried to test the board with the SDP board but it did not work. The software recognized both boards but the SPI communication didn't seem to work. In the program I was able to change the settings for the DAC as well as the contents of the input and DAC registers. These changes had no effect on the voltage output.

    Besides the LEDs for AVSS and AVDD the ALERT LED is also on. This one should only be on during the power-up state or after a full reset command. The initialization via the Raspberry pi or the SDP did not cause the LED to turn off.

    I have a second EVAL-AD5761RSDZ board that I tested with the SDP board. With this board, the ALERT LED went off after writing to the control register and I could measure a voltage. With the software I could also set other voltages. That is why I am assuming that the first board is broken.

    A control via the Raspberry Pi does not work with this board either. The maximum voltage of SPI communication with the Raspberry Pi I could measure were 3.3V, so that’s probably the reason why the ALERT LED stays on.

     

    Is there a possibility to set the DVcc voltage on the board lower so that the commands are recognized?

    Best regards,

    Nils

Reply
  • Hi Ian,

    Yes, the pins should be set high if not used but the value for it to be registered as high should be >0.7xDVcc as stated in the datasheet (Page 4, Logic Inputs VIH spec)

    This really seems to be the cause of the problem, but I also think the EVAL board is broken.

    I tried to test the board with the SDP board but it did not work. The software recognized both boards but the SPI communication didn't seem to work. In the program I was able to change the settings for the DAC as well as the contents of the input and DAC registers. These changes had no effect on the voltage output.

    Besides the LEDs for AVSS and AVDD the ALERT LED is also on. This one should only be on during the power-up state or after a full reset command. The initialization via the Raspberry pi or the SDP did not cause the LED to turn off.

    I have a second EVAL-AD5761RSDZ board that I tested with the SDP board. With this board, the ALERT LED went off after writing to the control register and I could measure a voltage. With the software I could also set other voltages. That is why I am assuming that the first board is broken.

    A control via the Raspberry Pi does not work with this board either. The maximum voltage of SPI communication with the Raspberry Pi I could measure were 3.3V, so that’s probably the reason why the ALERT LED stays on.

     

    Is there a possibility to set the DVcc voltage on the board lower so that the commands are recognized?

    Best regards,

    Nils

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